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LTC1658CS8 数据表(PDF) 3 Page - Linear Technology

部件名 LTC1658CS8
功能描述  14-Bit Rail-to-Rail Micropower DAC in MSOP
PDF  12 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC1658CS8 数据表(HTML) 3 Page - Linear Technology

  LTC1658CS8 Datasheet HTML 1Page - Linear Technology LTC1658CS8 Datasheet HTML 2Page - Linear Technology LTC1658CS8 Datasheet HTML 3Page - Linear Technology LTC1658CS8 Datasheet HTML 4Page - Linear Technology LTC1658CS8 Datasheet HTML 5Page - Linear Technology LTC1658CS8 Datasheet HTML 6Page - Linear Technology LTC1658CS8 Datasheet HTML 7Page - Linear Technology LTC1658CS8 Datasheet HTML 8Page - Linear Technology LTC1658CS8 Datasheet HTML 9Page - Linear Technology Next Button
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LTC1658
VCC = 2.7V to 5.5V, VOUT unloaded, REF ≤ VCC, TA = TMIN to TMAX, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance to GND
Input Code = 0
q
70
200
Ω
Output Line Regulation
Input Code = 16383, VCC = 2.7V to 5.5V, REF = 2.5V
q
1.5
mV/V
AC Performance
Voltage Output Slew Rate
q
0.35
1.0
V/
µs
Voltage Output Settling Time
(Note 3) to
±0.5LSB
12
µs
Digital Feedthrough
0.3
nV • s
Reference Input
RIN
REF Input Resistance
q
30
60
k
Ω
VREF
REF Input Range
(Notes 5, 6)
q
0VCC
V
Digital I/O
VIH
Digital Input High Voltage
VCC = 5V
q
2.4
V
VIL
Digital Input Low Voltage
VCC = 5V
q
0.8
V
VOH
Digital Output High Voltage
VCC = 5V, IOUT = – 1mA, DOUT Only
q
VCC – 0.7
V
VOL
Digital Output Low Voltage
VCC = 5V, IOUT = 1mA, DOUT Only
q
0.4
V
VIH
Digital Input High Voltage
VCC = 3V
q
2.0
V
VIL
Digital Input Low Voltage
VCC = 3V
q
0.6
V
VOH
Digital Output High Voltage
VCC = 3V, IOUT = – 1mA, DOUT Only
q
VCC – 0.7
V
VOL
Digital Output Low Voltage
VCC = 3V, IOUT = 1mA, DOUT Only
q
0.4
V
ILEAK
Digital Input Leakage
VIN = GND to VCC
q
±10
µA
CIN
Digital Input Capacitance
(Note 6)
q
10
pF
Switching (VCC = 4.5V to 5.5V)
t1
DIN Valid to CLK Setup
q
40
ns
t2
DIN Valid to CLK Hold
q
0ns
t3
CLK High Time
(Note 6)
q
40
ns
t4
CLK Low Time
(Note 6)
q
40
ns
t5
CS/LD Pulse Width
(Note 6)
q
50
ns
t6
LSB CLK to CS/LD
(Note 6)
q
40
ns
t7
CS/LD Low to CLK
(Note 6)
q
20
ns
t8
DOUT Output Delay
CLOAD = 15pF
q
5
100
ns
t9
CLK Low to CS/LD Low
(Note 6)
q
20
ns
Switching (VCC = 2.7V to 5.5V)
t1
DIN Valid to CLK Setup
q
60
ns
t2
DIN Valid to CLK Hold
q
0ns
t3
CLK High Time
(Note 6)
q
60
ns
t4
CLK Low Time
(Note 6)
q
60
ns
t5
CS/LD Pulse Width
(Note 6)
q
80
ns
t6
LSB CLK to CS/LD
(Note 6)
q
60
ns
t7
CS/LD Low to CLK
(Note 6)
q
30
ns
t8
DOUT Output Delay
CLOAD = 15pF
q
10
150
ns
t9
CLK Low to CS/LD Low
(Note 6)
q
30
ns



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