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LTC1685 数据表(PDF) 3 Page - Linear Technology |
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LTC1685 数据表(HTML) 3 Page - Linear Technology |
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3 / 12 page ![]() 3 LTC1685 DC ELECTRICAL CHARACTERISTICS VDD = 5V ±5%, unless otherwise noted. (Notes 2, 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RIN Input Resistance – 7V ≤ VCM ≤ 12V q 22 k Ω CIN Input Capacitance A, B Inputs, D, DE, RE 3 pF Open-Circuit Input Voltage, Figure 5 VDD = 5V (Note 4) q 3.2 3.3 3.4 V Fail-Safe Time to Detect Fail-Safe Condition 2 µs Time CMRR Receiver Input Common Mode VCM = 2.6V, f = 26MHz 45 dB Rejection Ratio CLOAD Receiver and Driver Output (Note 4) q 500 pF Load Capacitance VDD = 5V, unless otherwise noted. (Notes 2, 3) SWITCHING CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into the device pins are positive; all currents out of the device pins are negative. Note 3: All typicals are given for VDD = 5V, TA = 25°C. Note 4: Guaranteed by design, but not tested. Note 5: Short-circuit current does not represent output drive capability. When the output detects a short-circuit condition, output drive current is significantly reduced (from hundreds of mA to 20mA max) until the short is removed. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tPLH, tPHL Driver Input-to-Output Propagation Delay RDIFF = 54Ω, CL1 = CL2 = 100pF, q 15 18.5 22 ns Figures 3, 5 tSKEW Driver Output A-to-Output B Skew RDIFF = 54Ω, CL1 = CL2 = 100pF, 500 ps Figures 3, 5 tr, tf Driver Rise/Fall Time RDIFF = 54Ω, CL1 = CL2 = 100pF, 3.5 ns Figures 3, 5 tZH Driver Enable to Output High CL = 100pF, S2 Closed, Figures 4, 6 q 25 50 ns tZL Driver Enable to Output Low CL = 100pF, S1 Closed, Figures 4, 6 q 25 50 ns tLZ Driver Disable from Low CL = 15pF, S1 Closed, Figures 4, 6 q 25 50 ns tHZ Driver Disable from High CL = 15pF, S2 Closed, Figures 4, 6 q 25 50 ns tPLH, tPHL Receiver Input-to-Output Propagation Delay CL = 15pF, Figures 3, 7 q 15 18.5 22 ns tSQD Receiver Skew tPLH – tPHL CL = 15pF, Figures 3, 7 500 ps tZL Receiver Enable to Output Low CL = 15pF, S1 Closed, Figures 2, 8 q 25 50 ns tZH Receiver Enable to Output High CL = 15pF, S2 Closed, Figures 2, 8 q 25 50 ns tLZ Receiver Disable from Low CL = 15pF, S1 Closed, Figures 2, 8 q 25 50 ns tHZ Receiver Disable from High CL = 15pF, S2 Closed, Figures 2, 8 q 25 50 ns Maximum Receiver Input (Note 4) q 2000 ns Rise/Fall Times tPKG-PKG Package-to-Package Skew Same Temperature (Note 4) 1.5 ns Minimum Input Pulse Width VDD = 5V ± 5% (Note 4) q 17 19.2 ns Maximum Data Rate VDD = 5V ± 5% (Note 4) q 52 60 Mbps Maximum Input Frequency VDD = 5V ± 5% (Note 4) q 26 30 MHz |
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