LTC8043FS8 datasheet(3/4 Pages) LINER

3 / 4 page

LTC8043

ELECTRICAL CHARACTERISTICS

VDD = 5V, VREF = 10V, VIOUT = GND = 0V, TA = TMIN to TMAX, unless otherwise specified.

Note 7: To 0.01% for a full-scale change, measured from

falling edge of LD.

Note 8: VREF = 0V. DAC register contents changed from all 0s to all 1s or

from all 1s to all 0s.

Note 9: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s.

Note 10: 10Hz to 100kHz between RFB and IOUT. Calculation from en =

√4KTRB where: K = Boltzmann constant (J/K°); R = resistance (Ω);

T = resistor temperature (

°K); B = bandwidth (Hz).

BLOCK DIAGRAM

The q denotes specifications which apply over the full operating

temperature range.

Note 1:

±0.5LSB = ±0.012% of full scale.

Note 2: Using internal feedback resistor.

Note 3: Guaranteed by design, not subject to test.

Note 4: IOUT with DAC register loaded with all 0s.

Note 5: Typical temperature coefficient is 100ppm/

°C.

Note 6: IOUT load = 100Ω in parallel with 13pF.

40k

10k

40k

20k

40k

20k

40k

20k

40k

DECODER

BIT 1

(MSB)

BIT 2

BIT 3

BIT 4

BIT 12

(LSB)

CLK

LOAD

VDD

VREF

RFB

IOUT

SRI

GND

8043 BD

DAC REGISTER

INPUT 12-BIT SHIFT REGISTER

CLK

ALL GRADES

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Digital Inputs

VIH

Digital Input High Voltage

2.4

VIL

Digital Input Low Voltage

0.8

IIN

Digital Input Current

VIN = 0V to VDD

0.001

±1

µA

CIN

Digital Input Capacitance

VIN = 0V,(Note 3)

8pF

Timing Characteristics (Note 3)

tDS

Serial Input to Clock Setup Time

– 5

tDH

Serial Input to Clock Hold Time

tSRI

Serial Input Data Pulse Width

tCH

Clock Pulse Width High

tCL

Clock Pulse Width Low

tLD

Load Pulse Width

140

tASB

LSB Clocked into Input Register

0ns

to Load DAC Register Time

Power Supply

VDD

Supply Voltage

4.75

5.25

IDD

Supply Current

Digital Inputs = 0V or VDD

100

µA

Digital Inputs = VIH or VIN

500

µA

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

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