UPD78P324LP datasheet(13/80 Pages) NEC

13 / 80 page

µPD78P324, 78P324(A)

(2) Pins other than ports (2/2)

I/O

Output

Input

—

Input

—

Function

Access to external memory. Timing signal output for

externally latching the lower address which is output

from the AD0-AD7 pin.

Output of the signal which indicates that the watchdog

timer generated a non-maskable interrupt.

Normally, the EA pin is connected to VDD. By connecting

the EA pin to Vss, the system is placed in ROM-less mode

to access external memory. The level of the EA pin

cannot be switched over during operation.

Analog input to the A/D converter

Reference voltage input of the A/D converter.

Analog power of the A/D converter.

Ground of the A/D converter.

Input of the system reset.

Connection of the crystal oscillator for system clock

generation. When clocks are supplied externally, they are

input to the X1 pin and their reverse signals are input to

the X2 pin. (The X2 pin can also be left unconnected.)

Positive power voltage.

Ground.

Internally unconnected. Please connect this to Vss. (It can

also be left unconnected.)

Shared Pin Name

—

P70-P77

—

Pin Name

ASTB

WDTO

AN0-AN7

AVREF

AVDD

AVSS

RESET

VDD

VSS

1.2

PROM PROGRAMMING MODE (RESET = H, AVDD = L)

I/O

Input

I/O

Input

—

Function

PROM programming mode setting

Address bus

Data bus

Program input

PROM enable input

Read strobe to PROM

Write power

Positive power voltage

Ground

Internally unconnected. Please connect this to VSS. (It can also be left uncon-

nected.)

Pin Name

AVDD

RESET

A0-A16

D0-D7

PGM

VPP

VDD

VSS

UPD78P324LP 数据表(PDF) 13 Page - NEC

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UPD78P324LP 数据表(PDF) 13 Page - NEC

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