LS7060 datasheet(3/7 Pages) LSI

3 / 7 page

DYNAMIC ELECTRICAL CHARACTERISTICS:

(VDD = +5V ± 5%, VSS = 0V, TA = 0˚C to +70˚C unless otherwise noted.)

PARAMETER

SYMBOL

MIN

MAX

UNIT

CONDITIONS

Count Frequency

MHz

(All Count inputs)

Count Pulse Width

tCPW

Measured at 50% point,

(All Count Inputs)

Max tr, tf = 10ns

Count Rise & Fall time

tr, tf

µs

(Pins 1, 13)

Count Ripple Time

tCR

µs

Transition from 32 ones to 32 zeros

(Pins 1, 2 - LS7062)

from negative edge of count pulse

Count Ripple Time

tCR

µs

Transition of 16 bits from

(Pin 13 - LS7060)

all ones to all zeros from negative edge

(Pins 1,2,13 - LS7062)

of count pulse

Reset Pulse Width

tRPW

500

Measured at 50% point

(All Counter Stages

Max tr, tf = 200ns

Fully Reset)

RESET Removal Time

tRR

250

Measured from RESET signal at VIH

(Reset Removed From

All Counter Stages)

SCAN Frequency

fSC

MHz

SCAN Pulse Wildth

tSCPW

500

Measured at 50% point

Max tr, tf = 100ns

SCAN RESET/LOAD

tRSCPW

µs

Measured at 50% point

Pulse Width

Max tr, tf = 200ns

(All latches loaded and

Scan Counter Reset to

Least Significant Byte)

SCAN RESET/LOAD

tRSCR

250

Measured from SCAN RESET/

Removal Time

LOAD at VIH

(Reset Removed from

Scan Counter; Load

Command Removed

From Latches)

Output Disable

tDOD

200

Transition to Output High

Delay Time

Impedance State Measured

(B0 - B7)

From Scan at VIL or

ENABLE at VIH

Output ENABLE

tDOE

200

Transition to Valid On State

Delay Time

Measured from Scan at VIH

(B0 - B7)

and ENABLE at VIL; Delay to

Valid Data Levels for COL =10pF

and one TTL Load or Valid Data

Currents for High Capacitance Loads

Output Delay Time

tDCE

300

Negative Transition from Scan at VIL

CASCADE ENABLE

and ST5 of Scan Counter or Positive

Transition From SCAN RESET/LOAD at

VIL to Valid Data Levels for COL = 10pF

and one TTL Load

INPUT CURRENT

*SCAN RESET/LOAD

IIH

-2.5

µA

VDD = Max, VIH = +3.5

IIL

-5

µA

VDD = Max, VIL = 0

**All Count inputs

IIH

µA

VDD = Max, VIH = +3.5

IIL

µA

VDD = Max, VIL = 0

*Input has internal pull-up resistor to VDD

** Inputs have internal pull-down resistor to VSS

7060/62-071398-3

LS7060 数据表(PDF) 3 Page - LSI Computer Systems

LS7060 数据表(HTML) 3 Page - LSI Computer Systems

Html Pages

1 2 3 4 5 6 7

数据表下载

链接网址

LS7060 数据表(PDF) 3 Page - LSI Computer Systems

LS7060 数据表(HTML) 3 Page - LSI Computer Systems

Html Pages

1 2 3 4 5 6 7

数据表 下载

链接网址

数据表下载