SCAN COUNTER AND DECODER

The scan counter is reset to the least significant byte position

(State 1) when SCAN RESET input is brought low for a mini-

mum of 1µs. The scan counter is enabled for counting as long

as the ENABLE input is held low. The counter advances to the

next significant byte position on each negative transition of the

SCAN pulse. When the scan counter advances to State 6 it dis-

ables the Output Drivers and stops in that state until

SCAN RESET is again brought low.

SCAN

When the scan counter is enabled, each negative transition of

this input advances the scan counter to its next state. When

SCAN is low the Data Outputs are disabled. When SCAN is

brought high the Data Outputs are enabled and present the

latched counter data corresponding to the present state of the

scan counter. Therefore, in microprocessor applications, the

Data Output Bus may be utilized for other activities while new

data is propagating to the outputs. This positive SCAN pulse

can be viewed as a "Place the next byte on my bus" instruction

from the microprocessor. Minimum positive and negative pulse

widths of 500ns for the SCAN signal are required for scan

counter operation.

SCAN RESET/LOAD

When this input is brought low for a minimum of 1µs, the scan

counter is reset to State 1, the least significant byte position,

and the latches are simultaneously loaded with new count

information.

ENABLE

When this input is high, the scan counter and the Data Outputs are

disabled. When ENABLE is low, the scan counter and Data Out-

puts are enabled for normal operation. Transition of this input

should only be made while the SCAN input is in a low state in order

to prevent false clocking of the scan counter.

CASCADE ENABLE

This output is normally high. It transitions low and stays low when

the scan counter advances to State 6. In a multiple counter system

this output is connected to the ENABLE input of the next counter in

the cascade string. The SCAN input and SCAN RESET/LOAD in-

put are carried to all the counters in the "Cascade". Counter 1 then

presents its bytes of data to the Output Bus on each positive transi-

tion of the SCAN pulse as previously discussed. When State 6 of

Counter 1 is achieved, Counter 2 presents its data to the Output

Bus. This sequence continues until all counters in the cascade

have been addressed. See Figure 5 for an illustration of a 3 device

cascade design. This output is TTL and CMOS compatible.

THREE-STATE DATA OUTPUT DRIVERS

The eight Data Output Drivers are disabled when either ENABLE

input is high, the scan counter is in State 6, or the SCAN input is

low. The Output Drivers are TTL and Bus compatible.

7061/63-083198-2

valid

valid

valid

valid

LSB

LSB+1

LSB +2

LSB+3

FIGURE 3. SCAN COUNTER & DECODER OUTPUTS TIMING DIAGRAM

SCAN RESET

ENABLE

SCAN

ST1 (int.)

ST2 (int.)

ST3 (int.)

ST4 (int.)

ST5 (int.)

ENABLE (int.)

CASCADE ENABLE

DATA OUTPUTS

ENABLE (int.)

ST6 (int.)

valid

MSB