| 数据搜索系统,热门电子元器件搜索 |
|
LS7083 数据表(PDF) 1 Page - LSI Computer Systems |
|
|
|||||||||||||||||||||||||||||
LS7083 数据表(HTML) 1 Page - LSI Computer Systems |
|
1 / 4 page ![]() QUADRATURE CLOCK CONVERTER FEATURES: • x1 and x4 mode selection • Up to 16 MHz output clock frequency • Programmable output clock pulse width • On-chip filtering of inputs for optical or magnetic encoder applications. • TTL and CMOS compatible I/Os • +4.5V to +10.0V operation (VDD-VSS) • LS7083, LS7084 (DIP) LS7083-S, LS7084-S (SOIC) - See Figure 1 INPUT/OUTPUT DESCRIPTION: RBIAS (Pin 1) Input for external component connection. A resistor con- nected between this input and V SS adjusts the output clock pulse width (Tow). For proper operation, the output clock pulse width must be less than or equal to the A,B pulse separation (TOW ≤TPS). VDD (Pin 2) Supply Voltage positive terminal. VSS (Pin 3) Supply Voltage negative terminal. A (Pin 4) Quadrature Clock Input A. This input has a filter circuit to validate input logic level and eliminate encoder dither. B (Pin 5) Quadrature Clock Input B. This input has a filter circuit identical to input A. x4/x1 (Pin 6) This input selects between x1 and x4 modes of operation. A high-level selects x4 mode and a low-level selects the x1 mode. In x4 mode, an output pulse is generated for every transition at either A or B input. In x1 mode, an output pulse is generated in one combined A/B input cycle. (See Figure 2.) LS7083 - DNCK (Pin 7) In LS7083, this is the DOWN Clock Output. This output con- sists of low-going pulses generated when A input lags the B input. LS7084 - UP/DN (Pin 7) In LS7084, this is the count direction indication output. When A input leads the B input, the UP/DN output goes high indicating that the count direction is UP. When A input lags the B input, UP/DN output goes low, indicating that the count direction is DOWN. LS7083 - UPCK (Pin 8) In LS7083, this is the UP Clock output. This output consists of low-going pulses generated when A input leads the B in- put. LS7084 - CLK (Pin 8) In LS7084, this is the combined UP Clock and DOWN Clock output. The count direction at any instant is indicated by the UP/DN output (Pin 7). NOTE: For the LS7084, the timing of CLK and UP/DN re- quires that the counter interfacing with LS7084 counts on the rising edge of the CLK pulses. DESCRIPTION: The LS7083 and LS7084 are monolithic CMOS silicon gate quadrature clock converters. Quadrature clocks derived from optical or magnetic encoders, when applied to the A and B inputs of the LS7083/LS7084, are converted to strings of Up Clocks and Down Clocks (LS7083) or to a Clock and an Up/Down direction control (LS7084). These outputs can be interfaced directly with standard Up/Down counters for di- rection and position sensing of the encoder. October 2000 RBIAS VDD(+V) VSS(-V) A B x4/x1 DNCK UPCK PIN ASSIGNMENT - TOP VIEW CLK UP/DN FIGURE 1 1 2 3 4 8 7 6 5 RBIAS VDD(+V) VSS(-V) A B x4/x1 1 2 3 4 8 7 6 5 7083/84-100600-1 LSI/CSI LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 LS7083/7084 UL ® A3800 |
类似零件编号 - LS7083 |
|
类似说明 - LS7083 |
|
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |