FIGURE 2 . LOAD COUNTER, UP CLOCK, DOWN CLOCK, COMPARE OUT, CARRY, BORROW

NOTE 1: The counter in this example is assumed to be operating in the binary mode.

NOTE 2: No COMP output is generated here, although PR = CNTR. COMP output is disabled with a counter load command and

enabled with the rising edge of the next clock, thus eliminating invalid COMP outputs whenever the CNTR is loaded from the PR.

NOTE 3: When UP Clock is active, the DN Clock should be held "HIGH" and vice versa.

CNTR=FFFFFD

(PR=CNTR)

CNTR=FFFFFE CNTR=FFFFFF CNTR=000000

CNTR=000000

CNTR=FFFFFE

CNTR=0000001

CNTR=FFFFFD

(PR=CNTR)

CNTR=FFFFFF

NOTE 2

UP CLK (A)

DN CLK (B)

Q0

(Internal)

Q1

(Internal)

COMP

CY

BW

LTCR

Q2-Q23

(Internal)

UP CLK

OR DN CLK

CY

CYT

BW

BWT

COMP

COMPT

FIGURE 3. CLOCK TO CY/BW OUTPUT PROPAGATION DELAYS

SIGN

(INTERNAL)

7166-030192-7