Mode Select Inputs: A, B (Pin 5, Pin 6)

The four operating modes are selected by inputs A and B

according to Table 2.

TABLE 2. Mode Selection

A B

Mode

0

0

On-Delay (OND)

0

1

Off-Delay (OFD)

1

0

Dual-Delay (DLD)

1

1

One-Shot (OST)

Inputs A and B have internal pull-down resistors.

Driver Outputs: Out1, Out2 (Pin 13, Pin 12)

Out1 is an output for driving DC loads requiring high current sink,

such as relays, power transistors, etc. In steady-state condition

Out1, with the exception of one-shot mode, is always inverse in

polarity with respect to the Trigger input. Depending on the oper-

ating mode, the steady-state condition is reached immediately or

after a specified delay following a change of state at the Trigger

input. In one-shot mode, Out1 is always at logic high in the

steady state, independent of the logic state of the Trigger input.

Out2 operates in two different modes depending on the state of

the Flashen input.

If Flashen is at logic low then:

Out2 operates exactly as Out1 but with inverse polarity. In this

mode, Out2 is an output for driving DC loads requiring high cur-

rent source, such as relays, power transistors, etc. In steady-

state condition Out2, with the exception of one-shot mode, is al-

ways at the same polarity as the Trigger input. Depending on the

operating mode, the steady-state condition is reached immedi-

ately or after a specified delay following a change of state at the

Trigger input. In one-shot mode Out2 is always at logic low in the

steady state, independent of the logic state of the Trigger input.

If Flashen is at logic high then:

Out2 operates as a delay-in-progress indicator by generating pe-

riodic positive pulses during a delay timing. The pulse-rate, fpf

and the pulse-width tpf at Out2 is controlled by an internal os-

cillator whose frequency, fcf, is set by a capacitor connected to

the Cap input. fpf and fcf are related by the following expres-

sions:

fpf=20/fcf,

for scale factors 1x10

3

and 1x10

4

and

fpf=100/fcf,

for all other scale factors.

The pulse-width, tpf for both pulse-rates is given by:

tpf =2/fcf

At the end of timeout, Out2 returns to logic low with the cessation

of pulses.

Timer Start Input: Trigger (Pin 8)

Any logic transition at the Trigger input, positive or negative caus-

es the outputs Out1 and Out2 to switch with or without delay, de-

pending on the operating mode.

Any transition of the Trigger input also causes the logic states of

the following inputs to be strobed into internal latches: A, B, D1,

D2, D3 and Flashen. This prevents any changes at any of these

inputs from disrupting the timer when a timeout is in progress.

See the description of modes on Page1 and Out1, Out2 section

on Page 2 for a complete description of the Trigger input.

TheTrigger input has an internal pull-down resistor.

Flash Enable Input: Flashen (Pin 4)

The Flashen input modifies the operation of Out2 to function in

one of two modes.

When Flashen=0, Out2 functions exactly as Out1 but with inverse

polarity from Out1. When Flashen=1, Out2 functions as a flashing

delay-in-progress indicator. In this mode periodic positive pulses

are generated at Out2 during a delay timing which can be used to

produce a flashing LED display for user feedback. For a com-

plete description see Out2 section on Page 2. The Fashen input

has an internal pull-down resistor.

Master Clear Input: Reset (Pin 11)

When Reset is brought to logic high, all timing functions are

aborted, the timer is cleared, Out1 is forced high and Out2 is

forced low. Switching the Reset input low causes the mode select

inputs, the delay select inputs, the Flashen input and the Trigger

input to be sampled by internal logic. Following this, any in-

consistencies between the Trigger input and the Out1 and Out2

outputs are resolved and the steady state is reached with or with-

out delay based on the status of the mode select inputs. For ex-

ample, if the Trigger input is high, the Flashen input is low and

the mode is off-delay when the Reset input is switched from high

to low, Out1 and Out2 will immediately be switched low and high,

respectively, from its forced reset condition. In this example if the

mode is on-delay instead of off-delay, then Out1 and Out2 will be

switched after the completion of the programmed delay td.

It should be noted here that the states of Out1 and Out2 in the

reset condition and One-Shot mode steady state condition are

the same namely, Out1 = 1 and Out2 = 0. Because of this, in

one-shot mode, no change in Out1 and Out2 takes place when

the Reset input is switched low, irrespective of the status of the

Trigger input. The Reset input has an internal pull-down resistor

.

NOTE: A POR circuit (See Fig. 2) generates a reset upon power

up that produces the same conditions described for Reset

(Pin 11).

Timer Oscillator Input: RC (Pin 10)

A resistor-capacitor pair connected to the RC input serves as the

basic timing element for the delay timer oscillator.

The oscillator frequency is given by the expression:

frc=1/0.9RC,

where R and C are the resistor and the capacitor values at the

RC input.

The delay, td, is given by the expression:

td=s/frc,

where s is the scale factor selected by inputs D1, D2 and D3.

Flash Oscillator Input: Cap (Pin 9)

A capacitor, C, connected from the Cap input to ground regulates

an internal flash oscillator frequency according to the relation:

fcf=(k/C)x10

-6

controls the pulse-rate, fpf and the pulse width, tpf at Out2 in

flash mode according to the following relationships:

fpf=20/fcf,

fpf=100/fcf,

for all other scale factors; and for the pulse-width,

tpf=2/fcf, for all scale factors.

or ground terminal.

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