Datasheet

Datasheet

〇Product structure : Silicon monolithic integrated circuit 〇This product has no designed protection against radioactive rays

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TSZ02201-0L2L0H500270-1-2

© 2014 ROHM Co., Ltd. All rights reserved.

23.Mar.2015 Rev.002

TSZ22111 • 14 • 001

www.rohm.com

BU90T82

AC Characteristics

Table 3. Switching Characteristics（VDDIO=2.5V, VDD=1.8V, Ta=25℃, RL=100Ω, CL=5pF）

Symbol

Parameter

Limits

Units

Min

Typ

Max

Input CLK Period (Figure-4,5)

5.75

-

100

ns

CLK IN High Time (Figure -4,5)

ns

CLK IN Low Time (Figure -4,5)

ns

LVCMOS Data Set up to CLK IN (Figure -4,5)

0.8

-

-

ns

LVCMOS Data Hold from CLK IN (Figure -4,5)

0.8

-

-

ns

LVDS Transition Time (Figure -3)

-

0.6

1.5

ns

CLK OUT Period (Figure -6)

5.75

-

100

ns

Differential Output

Setup Time

CLKOUT=174MHz

-

-

120

ps

Differential Output

Hold time

CLKOUT=174MHz

-

-

120

ps

CLK IN to TCLK+/- Delay

(Figure-4,5)

MODE=L,DDRN=H

-

ns

Others

-

ns

Output Data Position 6 (Figure -6)

2

7

2

7

2

7

ns

Output Data Position 5 (Figure -6)

3

7

3

7

3

7

ns

Output Data Position 4 (Figure -6)

4

7

4

7

4

7

ns

Output Data Position 3 (Figure -6)

5

7

5

7

5

7

ns

Output Data Position 2 (Figure -6)

6

7

6

7

6

7

ns

Output Data Position 1 (Figure -6)

7

7

7

7

7

7

ns

Output Data Position 0 (Figure -6)

8

7

8

7

8

7

ns

Phase Locked Loop Set Time (Figure -7)

-

-

10

ms

DE input Period (Figure –10)

(Note2)

-

ns

DE High time (Figure -10)

(Note2)

-

ns

DE Low time (Figure -10)

-

-

ns

(Note2) m, n= integer、refer to Figure 10 (DE Input Timing Diagrams)

AC Timing Diagrams

Vdiff=(Tyx+)-(Tyx-)

Tyx+

Tyx-

CL

RL

LVDS Output

Load

80%

80%

20%

20%

Vdiff

x=1, 2

y=A,B,C,D,CLK

LVDS Output

Figure 3. LVDS Output AC Timing Diagrams