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RF2053

DS140110

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

Write

Initially ENX is high and SDATA is high impedance. The write operation begins with the controller starting SCLK. On the first fall-

ing edge of SCLK the baseband asserts ENX low. The second rising edge of SCLK is reserved to allow the SDI to initialize, and

the third rising edge is used to define whether the operation will be a write or a read operation. In write mode the baseband will

drive SDATA for the entire telegram. RF2053 will read the data bit on the rising edge of SCLK.

The next 7 data bits are the register address, MSB first. This is followed by the payload of 16 data bits for a total write mode

transfer of 24 bits. Data is latched into RF2053 on the last rising edge of SCLK (after ENX is asserted high).

For more information, please refer to the timing diagram on page 12.

The maximum clock speed for a register write is 19.2MHz. A register write therefore takes approximately 1.3us. The data is

latched on the rising edge of the clock. The datagram consists of a single start bit followed by a ‘0’ (to indicate a write opera-

tion). This is then followed by a seven bit address and a sixteen bit data word.

Note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional rising

clock edge before the ENX line is set low to ensure the address/data are read correctly.

Read

Initially ENX is high and SDATA is high impedance. The read operation begins with the controller starting SCLK. The controller is

in control of the SDATA line during the address write operation. On the first falling edge of SCLK the baseband asserts ENX low.

The second rising edge of SCLK is reserved to allow the SDI to initialize, and the third rising edge is used to define whether the

operation will be a write or a read operation. In read mode the baseband will drive SDATA for the address portion of the tele-

gram, and then control will be handed over to RF2053 for the data portion. RF2053 will read the data bits of the address on

the rising edge of SCLK. After the address has been written, control of the SDATA line is handed over to RF2053. One and a half

clocks are reserved for turn-around, and then the data bits are presented by RF2053. The data is set up on the rising edge of

SCLK, and the controller latches the data on the falling edge of SCLK. At the end of the data transmission, RF2053 will release

control of the SDATA line, and the controller asserts ENX high. The SDATA port on RF2053 transitions from high impedance to

low impedance on the first rising edge of the data portion of the transaction (for example, 3 rising edges after the last address

bit has been read), so the controller chip should be presenting a high impedance by that time.

For more information, please refer to the timing diagram on page 12.

The maximum clock speed for a register read is 19.2MHz. A register read therefore takes approximately 1.4us. The address is

latched on the rising edge of the clock and the data output on the falling edge. The datagram consists of a single start bit fol-

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ENX

SCLK

SDATA

XA6

A5

A4

A3

A2

A1

A0

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ENX

SCLK

SDATA

XA6

A5