Preliminary Datasheet

LP6205S

LP6205S–00 Ver. 1.0 Datasheet

Jul.-2013

www.lowpowersemi.com

Page 4 of 5

Application Information

Referring to Typical application circuits, the output

voltage of the switching regulator(Vout) can be set with

Equation(1):

Vout=(1+R1/R2) X 1.25 V

Feedback Loop Design

Referring to the typical application circuits, the

selection of R1 and R2 based on the trade-off between

quiescent current consumption and interference

immunity is stated below:

For applications without standby or suspend modes,

lower values of R1 and R2 are preferred. For

applications concerning the current consumption in

standby or suspend modes, the higher values of R1

and R2 are needed. Such high impedance, which

requires careful PCB layout and avoid any

interference.

Especially to FB pin. To improve the system stability a

proper value capacitor between FB pin and GND pin is

suggested. An empirical suggestion is around 220pF.

PCB Layout Guide

PCB Layout shall follow these guidelines for better

system stability:

1. A full GND plane without any gap break.

2. VDD to GND bypass Cap-The 1uF MLCC noise

bypass cap pin4 shall have short and wide

connections.

3. Vin to GND bypass Cap-Add a Cap close to the

inductor when Vin is not an idea voltage source.

4. Minimize the FB node copper area and keep it far

away from noise sources.

5. I follow Equation(1)

6. I Higher R reduces the quiescent current(Path

current=1.25V/R2),however resistors beyond

5M/W are not recommended.