Improved, Quad,

SPST Analog Switches

_______________________________________________________________________________________

7

tr < 20ns

tf < 20ns

50%

0V

LOGIC

INPUT

V-

-15V

300

Ω

D1

GND

(

)

SWITCH

INPUT

IN1

+3V

0V

SWITCH OUTPUT

SWITCH

OUTPUT

LOGIC

INPUT

LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

V+

35pF

+5V

+15V

S1

0V

REPEAT TEST FOR IN AND S, FOR LOAD

CONDITIONS, SEE Electrical Characteristics.

DG411

DG412

DG413

50%

0.9 x VOUT1

+3V

0V

0V

LOGIC

INPUT

SWITCH

OUTPUT 2

(VO2)

0V

0.9 x VOUT2

tD

tD

LOGIC

INPUT

V-

-15V

GND

S2

IN

S1

V+

+5V

+15V

Ω

D1

D2

SWITCH

OUTPUT 1

(VO1)

DG413

Figure 2. Switching-Time

Figure 3. DG413 Break-Before-Make

______________________________________________Timing Diagrams/Test Circuits

VGEN

GND

D

CL

VOUT

-15V

V-

V+

VOUT

IN

OFF

ON

OFF

∆VOUT

Q = (

∆VOUT)(CL)

S

+5V

IN DEPENDS ON SWITCH CONFIGURATION;

INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

OFF

ON

OFF

IN

+15V

IN

DG411

DG412

DG413

Figure 4. Charge-Injection