MAX1005EEE datasheet(4/8 Pages) MAXIM

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CONDITIONS

IF Undersampler

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ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCD = 3.0V, fCLK = 15MHz, RL = ∞, TA = TMIN to TMAX, unless otherwise noted.)

RXEN, TXEN;

VCCD = 2.7V

to 3.6V

D0–D6, CLK; VCCD = 2.7V to 5.5V

CL ≤ 12.5pF

TA = +25°C (Note 6)

RXEN, TXEN;

VCCD = 3.6V

to 5.5V

D0–D6, CLK; TXEN = 1, RXEN = 0 (Note 6)

CONDITIONS

±2

±1

µA

-1

IIN

Input Current

tDO

ADC CLK to Output Data Valid

CLK Duty Cycle

0.3

tHOLD

DAC Data Hold Time

0.6

tDS

DAC Data Setup Time

±1

±4

CIN

Input Capacitance

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

TXEN = 0 and RXEN = 1, or

TXEN = 1 and RXEN = 0

TXEN = RXEN

TXEN = 0 and RXEN = 1, or

TXEN = 1 and RXEN = 0

Note 1:

TXEN = 1, RXEN = 0. All DAC transfer function parameters are measured differentially from AIO+ to AIO- using the End-

Point Linearity method.

Note 2:

fIN = 4.3MHz digital sine wave applied to DAC data inputs; fCLK = 15MHz. The reference frequency (fREF) is defined to be

10.7MHz (fCLK - fIN). All frequency components present in the DAC output waveform except for fREF and fIN are consid-

ered spurious.

Note 3:

For DAC SFDR measurements, the amplitude of fREF (10.7MHz) is compared to the amplitudes of all frequency compo-

nents of the output waveform except for fIN (4.3MHz).

Note 4:

For DAC measurements, THD+N is defined as the ratio of the square-root of the sum-of-the-squares of the RMS values of

all harmonic and noise components of the output waveform (except for fIN and fREF) to the RMS amplitude of the fREF com-

ponent.

Note 5:

Clock feedthrough is defined as the difference in amplitude between the fREF component and the fCLK component when

measured differentially from AIO+ to AIO-.

Note 6:

Guaranteed by design. Not production tested.

Note 7:

The DAC input interface is a master/slave register. An additional half clock cycle is required for data at the digital inputs to

propagate through to the DAC switches.

Note 8:

RXEN = 1, TXEN = 0. Unless otherwise noted, for all receive ADC measurements, the analog input signal is applied differ-

entially from AIO+ to AIO-, specified using the Best-Fit Straight-Line Linearity method.

Note 9:

fIN = 10.7MHz, fCLK = 15MHz. Amplitude is 1dB below full-scale. The reference frequency (fREF) is defined to be 4.3MHz

(fCLK - fIN). All components except for fREF and fIN are considered spurious.

Note 10: Receive ADC THD measurements include the first five harmonics.

Note 11: CAUTION: Operation of the analog inputs AIO+ and AIO- (pins 4 and 5) at more than 1.5V below VCCA could cause

latchup and possible destruction of the part. Avoid shunt capacitances to GND on these pins. If shunt capacitances are

required, then bypass these pins only to VCCA.

Note 12: All digital input signals are measured from 50% amplitude reference points. All digital output signal propagation delays are

measured to VOH(AC) for rising output signals and to VOL(AC) for falling output signals. The values for VOH(AC) and VOL(AC)

as a function of the VCCD supply are shown in the following table:

VCCD (V)

VOH(AC) (V)

VOL(AC) (V)

2.7 to 3.3

VCCD - 1.1

0.5

3.3 to 5.5

2/3 x VCCD

0.5

TIMING CHARACTERISTICS (Data Outputs: RL = 1MΩ, CL = 15pF, TA = TMIN to TMAX, unless otherwise noted.) (Note 12)

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