CMOS High-Speed 8-Bit ADCs with

Multiplexer and Reference

6

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_______________Detailed Description

Converter Operations

The MAX154/MAX158 use what is commonly called a

"half-flash" conversion technique (Figure 3). Two 4-bit

flash ADC converter sections are used to achieve an 8-

bit result. Using 15 comparators, the upper 4-bit MS

(most significant) flash ADC compares the unknown

input voltage to the reference ladder and provides the

upper four data bits.

An internal DAC uses the MS bits to generate an analog

signal from the first flash conversion. A residue voltage

representing the difference between the unknown input

and the DAC voltage is then compared to the reference

ladder by 15 LS (least significant) flash comparators to

obtain the lower four output bits.

Operating Sequence

The operating sequence is shown in Figure 4. A conver-

sion is initiated by a falling edge of RD and CS. The

comparator inputs track the analog input voltage for

approximately 1µs. After this first cycle, the MS flash

result is latched into the output buffers and the LS con-

version begins. INT goes low approximately 600ns later,

indicating the end of the conversion, and that the lower

four bits are latched into the output buffers. The data

can then be accessed using the CS and RD inputs.

___________________Digital Interface

The MAX154/MAX158 use only Chip Select (CS) and

Read (RD) as control inputs. A READ operation, taking

CS and RD low, latches the multiplexer address inputs

and starts a conversion (Table 1).

There are two interface modes, which are determined

by the length of the RD input. Mode 0, implemented by

keeping RD low until the conversion ends, is designed

for microprocessors that can be forced into a WAIT

state. In this mode, a conversion is started with a READ

operation (taking CS and RD low), and data is read

when the conversion ends. Mode 1, on the other hand,

does not require microprocessor WAIT states. A READ

operation simultaneously initiates a conversion and

reads the previous conversion result.

4-BIT

DAC

THREE-

STATE

DRIVERS

ADDRESS

LATCH

DECODE

4-BIT

FLASH

ADC

(4LSB)

4-BIT

FLASH

ADC

(4MSB)

2.5V

REF

TIMING AND CONTROL

CIRCUITRY

MUX*

16

A0

*MAX154 – 4-Channel Mux

MAX158 – 8-Channel Mux

A1

A2

RDY

CS

RD

AIN1

AIN4

AIN8

REF OUT

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

INT

MAX154/MX7824

A1

A0

MAX158/MX7828

A2

A1

A0

SELECTED

CHANNEL

00

01

10

11

00

0

00

1

01

0

01

1

AIN1

AIN2

AIN3

AIN4

Figure 3. Functional Diagram

Table 1. Truth Table for Input Channel

Selection

10

0

10

1

11

0

11

1

AIN5

AIN6

AIN7

AIN8