Ver1.1

10

LD3003

128 Segment LCD Controller and Driver

SERIAL DATA TRANSFER FORMAT

WHEN ENB PIN IS FIXED TO VDD

b) Continuous Transfer Case

a) 128 bit Data Only Transfer Case

DCLK

START

8 bits Address

128 bits Data

STOP

Internal Data

Latch Signal

DIN

COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1

COM4 COM3 COM2 COM1

SEG1

SEG2

SEG32

DCLK

START

8 bits Address

128 bits Data

Internal Data

Latch Signal

Next 128 bits Data

DIN

COM4 COM3 COM2 COM1

COM4 COM3 COM2 COM1

COM4 COM3 COM2 COM1

SEG1

SEG32

SEG1

Before communication with LD3003 can begin, a start condition must be set up on the bus by the transmitter. To

establish a start condition, the transmitter must pull the data line( DIN ) low for at least one clock-pulse time while

the clock line( DCLK ) is high. The “idle” state for the clock line and data line is the high state. After the start

condition has been established, an 8 bits address( 01111110 ) should be sent by the transmitter. If the address

sent corresponds to the address of LD3003 then on each successive clock pulse, the addressed device will accept

a data bit.

If the ENB pin is permanently high, then the addressed LD3003’s internal counter latches the data to be displayed

after 128 data bits have been received. Otherwise, the control of this latch function may be overridden by holding

the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line.

The high pulse must be sent during DCLK high( clock idle ). To end communication with LD3003, a stop condition

should be setup on the bus( or another start condition maybe set up if another communication is desired. ).

To establish a stop condition, the transmitter must pull the data line high for at least one clock-pulse time while the

clock line is high.