Precision, Quad, SPST Analog Switches

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7

tOFF

0.8VO

VO

0.8VO

50%

0V

0V

+3V

SWITCH

INPUT

SWITCH

OUTPUT

LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

tON

SWITCH

INPUT

LOGIC

INPUT

+3V

1N_

COM_

+15V

V+

V-

-15V

RL

35pF

VO

NO_ OR NC_

FOR LOAD CONDITIONS, SEE SPECIFICATIONS

CL (INCLUDES FIXTURE AND STRAY CAPACITANCE)

GND

REPEAT TEST FOR CHANNELS 2, 3, AND 4.

VO = VCOM

RL

LOGIC

INPUT

∆VO

OFF

ON

OFF

VO

IN_

MAX361

IN_

MAX362

OFF

OFF

ON

Q =

∆VO × CL

-15V

V-

V+

IN_

GND

COM_

+15V

RGEN

VGEN

VIN = +3V

CL

VO

NO_

OR NC_

ANALYZER

SIGNAL

GENERATOR

RGEN = 50Ω

0.8V, 2.4V

NC1 OR NO1

IN1

COM2

GND

RL

10dBm

C

V+

+15V

COM1

IN2

NC2 OR NO2

0.8V, 2.4V

50

Ω

V-

-15V

C

ANALYZER

SIGNAL

GENERATOR

RGEN = 50Ω

NC_ OR

NO_

COM

GND

RL

10dBm

C

V+

+15V

IN_

0.8V, 2.4V

V-

-15V

C

Figure 1. Switching-Time Test Circuit

Figure 2. Charge-Injection Test Circuit

Figure 3. Crosstalk Test Circuit (repeat for channels 3 and 4)

Figure 4. Off-Isolation Test Circuit