Setting the Higher-Order Poles

Spurious noise is generated by the phase detector

digital phase detector by placing a higher-order pole

(HOP) at a frequency much less than the compare fre-

quency. The HOP should, however, be placed high

enough in frequency that it does not decrease the over-

all loop-phase margin and impact jitter peaking. These

two conditions can be met by selecting the HOP fre-

the loop bandwidth.

The HOP can be implemented either by providing a

directly on the VCO tuning port, which produces a pole at:

noise in the PLL, but it might still be necessary to provide

Setting the Optional Output

The MAX3672 optional clock output can be set to binary

subdivisions of the main clock frequency. The PSEL1

and PSEL2 pins control the binary divisions. Table 5

shows the pin configuration and possible divider ratios.

Applications Information

PECL Interfacing

The MAX3672 outputs (MOUT+, MOUT-, POUT+,

POUT-) are designed to interface with PECL signal levels

and should be biased appropriately. Proper termination

requires an external circuit that provides a Thevenin

equivalent of 50

Ω to VCC - 2.0V and controlled-imped-

ance transmission lines. To ensure best performance,

the differential outputs must have balanced loads. If the

optional clock output is not used, the output can be left

floating to save power.

Layout

The MAX3672 performance can be significantly affected

by circuit board layout and design. Use good high-

frequency design techniques, including minimizing

ground inductance and using fixed-impedance trans-

mission lines on the reference and VCO clock signals.

Power-supply decoupling should be placed as close to

the die as possible. Take care to isolate the input from

the output signals to reduce feedthrough.

VCO Selection

The MAX3672 is designed to accommodate a wide

range of VCO gains, positive or negative transfer

trol voltages. These features allow the user a wide

range of options in VCO selection; however, the proper

VCO must be selected to allow the clock generator cir-

cuitry to operate at the optimum levels. When selecting

f

RC

π

1

2

33

f

kC

HOP

()(

)

=

πΩ

1

220

2

Low-Jitter 155MHz/622MHz Clock Generator

_______________________________________________________________________________________

9

INPUT PIN NSEL1 INPUT PIN NSEL2

1

OPEN

2

GND

4

OPEN

8

OPEN

OPEN

16

GND

OPEN

32

GND

64

OPEN

GND

128

GND

GND

256

Table 3. Divider Logic Setup

INPUT PIN

VSEL

VCO DIVIDER

N1

INPUT PIN

RSEL

REFERENCE-

CLOCK

DIVIDER N3

1

OPEN

8

OPEN

2

GND

32

GND

8

Table 2. RSEL and VSEL Settings

INPUT PIN GSEL

Kpd (µA/UI)

20

GND

5

Table 4. Phase Detector Gain Setup

INPUT PIN

PSEL1

INPUT PIN

PSEL2

VCO TO POUT

DIVIDER RATIO

1

GND

2

GND

4

GND

GND

8

Table 5. Optional Clock Setup