9DB1233 datasheet(7/15 Pages) ICST

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IDT® Twelve Output Differential Buffer for PCIe Gen3

9DB1233

Twelve Output Differential Buffer for PCIe Gen3

1675B—11/08/10

Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics

TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

-3dB point in High BW Mode

MHz

-3dB point in Low BW Mode

0.7

1.4

MHz

PLL Jitter Peaking

tJPEAK

Peak Pass band Gain

1.5

Duty Cycle

tDC

Measured differentially, PLL Mode

49.5

Duty Cycle Distortion

tDCD

Measured differentially, Bypass Mode @100MHz

-2

1,4

tpdBYP

Bypass Mode, VT = 50%

2500

4500

tpdPLL

PLL Mode VT = 50%

-250

250

Skew, Output to Output

tsk3

VT = 50%

PLL mode

1,3

Additive

Jitter in Bypass Mode

1,3

1Guaranteed by design and characterization, not 100% tested in production.

2 I

REF = VDD/(3xRR). For RR = 475

(1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50 .

3 Measured from differential waveform

4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

Skew, Input to Output

Jitter, Cycle to cycle

tjcyc-cyc

PLL Bandwidth

Electrical Characteristics - PCIe Phase Jitter Parameters

TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

tjphPCIeG1

PCIe Gen 1

ps (p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

1.1

(rms)

1,2

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

2.2

3.1

(rms)

1,2

tjphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.4

(rms)

1,2,4,5

tjphPCIeG1

PCIe Gen 1

ps (p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.5

0.6

(rms)

1,2,6

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.8

(rms)

1,2,6

tjphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.35

0.5

(rms)

1,2,4,5,

1 Applies to all outputs when driven by 932SQ420DGLF or equivalent.

6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter) = SQRT{(total jittter)^2 - (input jitter)^2}

4 Subject to final radification by PCI SIG.

tjphPCIeG2

2 See http://www.pcisig.com for complete specs

tjphPCIeG2

Phase Jitter, PLL Mode

Additive Phase Jitter,

Bypass Mode

5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.4

3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

9DB1233 数据表(PDF) 7 Page - Integrated Circuit Systems

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