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9FGL02 数据表(PDF) 13 Page - Integrated Device Technology

部件名 9FGL02
功能描述  control input polarity
PDF  19 Pages
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制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology

9FGL02 数据表(HTML) 13 Page - Integrated Device Technology

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REVISION A 07/17/15
13
2-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR
9FGL02 DATASHEET
SMBus Table: Stop State Control
Byte 11
Name
Control Function
Type
0
1
Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
STP[1]
RW
00 = Low/Low
10 = High/Low
0
Bit 0
STP[0]
RW
01 = HiZ/HiZ
11 = Low/High
0
SMBus Table: Impedance Control
Byte 12
Name
Control Function
Type
0
1
Default
Bit 7
DIF0_imp[1]
DIF0 Zout
RW
00=33 DIF Zout
10=100 DIF Zout
Bit 6
DIF0_imp[0]
DIF0 Zout
RW
01=85 DIF Zout
11 = Reserved
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
SMBus Table: Impedance Control
Byte 13
Name
Control Function
Type
0
1
Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
DIF1_imp[1]
DIF1 Zout
RW
00=33 DIF Zout
10=100 DIF Zout
Bit 2
DIF1_imp[0]
DIF1 Zout
RW
01=85 DIF Zout
11 = Reserved
Bit 1
X
Bit 0
X
SMBus Table: Pull-up Pull-down Control
Byte 14
Name
Control Function
Type
0
1
Default
Bit 7
OE0_pu/pd[1]
RW
00=None
10=Pup
0
Bit 6
OE0_pu/pd[0]
RW
01=Pdwn
11 = Pup+Pdwn
1
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
SMBus Table: Pull-up Pull-down Control
Byte 15
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
1
Bit 5
0
Bit 4
1
Bit 3
OE1_pu/pd[1]
RW
00=None
10=Pup
0
Bit 2
OE1_pu/pd[0]
RW
01=Pdwn
11 = Pup+Pdwn
1
Bit 1
0
Bit 0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
See Note
See Note
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OE0 Pull-up(PuP)/
Pull-down(Pdwn) control
Reserved
Reserved
OE1 Pull-up(PuP)/
Pull-down(Pdwn) control
Reserved
Reserved
Reserved
Reserved
Reserved
True/Complement DIF Output
Disable State
Reserved
Reserved



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