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DATA SHEET #: ____________ PAGE______ OF _______ REV:________ DATE:____________

CONNOR

WINFIELD

© Copyright 2000 Connor-Winfield all rights reserved.

Specifications subject to change without notice.

TM000

1/3/2000

04

NETWORK ELEMENT TIMING GENERATOR

STRATUM 3 SIMPLIFIED CONTROL

TIMING MODULES (STM-S3)

INT

1

6

DESCRIPTION

The Connor-Winfield Stratum 3 Simplified Control

Timing Module acts as a complete system clock module for general

Stratum 3 timing applications. The STM is designed for external

control functions. Full external control input allows for selection

and monitoring of any of four possible operating states: 1)

Holdover, 2) External Reference #1, 3) External Reference #2, and

4) Free Run. The table below illustrates the control signal inputs

and corresponding operational states:

In the absence of External Control Inputs (A,B), the STM

enters the Free Run mode and signals an External Alarm. The

STM will enter other operating modes upon application of a proper

control signal. Mode 1 operation (A=1, B=0) results in an output

signal that is phase locked to the External Reference Input #1.

Mode 2 operation (A=0, B=1) results in an output signal that is

phase locked to External Reference Input #2. Holdover mode

operation (A=1, B=1) results in an output signal at or near the

frequency as determined by the latest (last) locked-signal input

values and the holdover performance of the STM.

Alarm signals are generated at the Alarm Output during

Holdover and Free Run operation. Alarm Signals are also

generated by loss-of-lock, loss of Reference, and by a Tune-Limit

indication from the PLL. A Tune-Limit alarm signal indicates

that the VCXO tuning voltage is approaching within 10% the limits

of its lock capability and that the External Reference Input may

be erroneous. A high level indicates an alarm condition. Real-

time indication of the operational mode is available at unique

operating mode outputs on pins 1-4.

Control loop filters effectively attenuate any reference

jitter and smooth out phase transients.

BLOCK DIAGRAM

STM-S3

CNTL A

CNTL B

STM-S3 PIN ASSIGNMENT

HLDOVR

REF 1

REF 2

FRERUN

GND

ALARM OUT

CNTL A

CNTL B

N/C

N/C

N/C

N/C

+5Vdc

EX REF 1

GND

EX REF 2

GND

SYNC_OUT

GND

PLL TVL

N/C

GND

CLK_OUT

N/C

BOTTOM VIEW

L

O

R

T

N

O

C

T

U

P

N

I

E

D

O

M

L

A

N

O

I

T

A

R

E

P

O1

F

E

R2

F

E

RR

V

O

D

L

HN

U

R

E

R

F*

L

V

T

_

L

L

P

M

R

A

L

A

T

U

P

T

U

O

AB

00

)t

l

u

a

f

e

D

(

n

u

R

e

e

r

F

000

1

0

1

10

l

a

n

r

e

t

x

E

e

c

n

e

r

e

f

e

R

1

#

l

a

m

r

o

N

ti

m

i

L

e

n

u

T

L

O

L

+

S

O

L

1

1

1

0

0

0

0

0

0

0

0

0

0

1

0

0

1

1

01

l

a

n

r

e

t

x

E

e

c

n

e

r

e

f

e

R

2

#

l

a

m

r

o

N

ti

m

i

L

e

n

u

T

L

O

L

+

S

O

L

0

0

0

1

1

1

0

0

0

0

0

0

0

1

0

0

1

1

11

r

e

v

o

d

l

o

H0

0

1

0

0

1

2:4

0

1

2

3

HOLDOVER

REF 1

REF 2

FRERUN

EXREF1

EXREF2

2:1

MUX

STRATUM3

VCXO

DAC

FILTERS

PHASE

COMPARATOR

CLK_OUT

SYNC_OUT

PLL TVL

ALARM OUT

TUNING

VOLTAGE

MONITOR

STRATUM3

TCXO

DAC

FIFO

2:1

MUX

PLL TVL

FREE RUN

HOLDOVER

LOCK AND

DETECTION