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FT232H 数据表(PDF) 21 Page - Future Technology Devices International Ltd. |
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FT232H 数据表(HTML) 21 Page - Future Technology Devices International Ltd. |
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21 / 65 page  Copyright © 2014 Future Technology Devices International Limited 21 Document No.: FT_000288 FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC Datasheet Version 1.81 Clearance No.: FTDI #199 3.5.8 FT232H Pins Configured as a FT1248 Interface The FT232H can be configured as a proprietary FT1248 interface. This mode is enabled in the external EEPROM. When configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.13. Pin No. Name Type UART Configuration Description 13 MIOSIO0 INPUT /OUTPUT Bi-directional synchronous command and data bus, bit 0 used to transmit and receive data from/to the master 14 MIOSIO1 INPUT /OUTPUT Bi-directional synchronous command and data bus, bit 1 used to transmit and receive data from/to the master 15 MIOSIO2 INPUT /OUTPUT Bi-directional synchronous command and data bus, bit 2 used to transmit and receive data from/to the master 16 MIOSIO3 INPUT /OUTPUT Bi-directional synchronous command and data bus, bit 3 used to transmit and receive data from/to the master 17 MIOSIO4 INPUT /OUTPUT Bi-directional synchronous command and data bus, bit 4 used to transmit and receive data from/to the master 18 MIOSIO5 INPUT /OUTPUT Bi-directional synchronous command and data bus, bit 5 used to transmit and receive data from/to the master 19 MIOSIO6 INPUT /OUTPUT Bi-directional synchronous command and data bus, bit 6 used to transmit and receive data from/to the master 20 MIOSIO7 INPUT /OUTPUT Bi-directional synchronous command and data bus, bit 7 used to transmit and receive data from/to the master 21 SCLK INPUT Serial clock used to drive the slave device data 27 SS_n INPUT Active low slave select 0 from master to slave 28 MISO OUTPUT Slave output used to transmit the status of the transmit and receive buffers are empty and full respectively Table 3.13 FT1248 Configured Pin Descriptions For functional description of this mode, please refer to section 4. |
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