DATASHEET

ZERO DELAY, LOW SKEW BUFFER

ICS574

IDT™/ ICS™ ZERO DELAY, LOW SKEW BUFFER

1

ICS574

REV G 051310

Description

The ICS574 is a low jitter, low-skew, high performance

PLL-based zero delay buffer for high speed applications.

Based on IDT’s proprietary low jitter Phase Locked Loop

(PLL) techniques, the device provides four low skew

outputs at speeds up to 160 MHz at 3.3 V. When one of the

outputs is connected directly to FBIN, the rising edge of

each output is aligned with the rising edge of the input

clock. External delay elements connected in the feedback

loops will cause the outputs to occur before the inputs by

the amount of propagation delay of the external element.

Features

clock generators

TTL levels at 3.3 V

Block Diagram

PLL

FBIN

CLKIN

CLK1

CLK2

CLK3

CLK4