Quad, Low-Voltage, SPST Analog Switches

_______________________________________________________________________________________

5

Note 3:

The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.

Note 4:

Guaranteed by design.

Note 5:

Note 6:

Resistance flatness is defined as the difference between the maximum and minimum on-resistance values, as measured

over the specified analog signal range.

Note 7:

Note 8:

Note 9:

Between any two switches.

Note 10: Leakage testing for single-supply operation is guaranteed by testing with dual supplies.

ELECTRICAL CHARACTERISTICS—Single +3V Supply

+25°C

(Note 4)

COM_ to NO_, COM_ to NC_

On-Resistance

C, E, M

600

Ω

IN_ Input Logic Threshold High

C, E

1.6

2.4

V

IN_ Input Logic Threshold Low

CONDITIONS

C, E, M

260

500

V

0

V+

Analog Signal Range

C, E

0.8

1.6

V

IN_ Input Current Logic High

or Low

C, E

-1

0.03

1

µA

+25°C

120

250

Turn-On Time

Figure 1

C, E, M

300

ns

+25°C

40

80

Turn-Off Time

Figure 1

C, E, M

100

ns

+25°C

15

50

Break-Before-Make Time Delay

(MAX4523 Only)

Figure 2

ns

+25°C

-1

0.05

1

V+ Supply Current

UNITS

MIN

TYP

MAX

(Note 3)

SYMBOL

PARAMETER

I+

C, E, M

-1

1

µA

+25°C

-1

0.05

1

V- Supply Current

I-

V- = 0V

C, E, M

-1

1

µA

Charge Injection

Q

Figure 3

+25°C

0.5

5

pC

ANALOG SWITCH

LOGIC INPUT

SWITCH DYNAMIC CHARACTERISTICS (Note 4)

POWER SUPPLY