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MAX504CSD 数据表(PDF) 5 Page - Maxim Integrated Products |
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MAX504CSD 数据表(HTML) 5 Page - Maxim Integrated Products |
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5 / 16 page ![]() 5V, Low-Power, Voltage-Output, Serial 10-Bit DACs _______________________________________________________________________________________ 5 Note 2: In single-supply operation, INL and GE calculated from Code 3 to Code 1023. Note 3: Guaranteed by design. Note 4: Tested at IOUT = 100µA. The reference can typically source up to 5mA (see Typical Operating Characteristics). Note 5: The timing characteristics limits for the MAX515 are guaranteed by design. ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (MAX504 Only) (continued) (VDD = 5V, VSS = -5V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, CREFOUT = 33µF, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL MIN TYP MAX UNITS Voltage-Output Slew Rate SR dB 0.15 0.25 VDD V/µs 4.5 5.5 ISC 12 V mA Positive Supply Voltage 0.5 LSB Negative Supply Voltage Voltage-Output Settling Time 16 µs Signal-to-Noise Plus Distortion 5 nV-s VSS -5.5 0 V Short-Circuit Current 68 Digital Feedthrough SINAD 68 Output Load Regulation VSS + 2 VDD - 2 Output Voltage Range VSS + 0.4 VDD - 0.4 V CONDITIONS VOUT = 2V, RL = 2kΩ To ±1/2LSB, VOUT = 2V Step all 0s to all 1s REFIN = 1kHz, 2Vp-p (G = 1) REFIN = 1kHz, 2Vp-p (G = 2) (G = 1) (G = 2) CS Setup Time tCSS 20 ns SCLK Fall to CS Fall Hold Time tCSH0 15 ns SCLK Fall to CS Rise Hold Time tCSH1 0 ns SCLK High Width tCH 35 ns SCLK Low Width tCL 35 ns DIN Setup Time tDS 45 ns DIN Hold Time tDH 0 ns DOUT Valid Propagation Delay tDO CL = 50pF 80 ns CS High Pulse Width tCSW 20 ns CLR Pulse Width tCLR 25 ns CS Rise to SCLK Rise Setup Time tCS1 50 ns Positive Supply Current IDD 260 400 µA All inputs = 0V or VDD, no load Negative Supply Current ISS -120 -200 µA All inputs = 0V or VDD, no load VOLTAGE OUTPUT (VOUT) DYNAMIC PERFORMANCE POWER SUPPLY SWITCHING CHARACTERISTICS |
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