MAX542ACPD datasheet(3/12 Pages) MAXIM

3 / 12 page

+5V, Serial-Input, Voltage-Output, 16-Bit DACs

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ELECTRICAL CHARACTERISTICS (continued)

(VDD = +5V ±5%, VREF = +2.5V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)

TIMING CHARACTERISTICS

(VDD = +5V ±5%, VREF = +2.5V, AGND = DGND = 0, CMOS inputs, TA = TMIN to TMAX, unless otherwise noted.)

Note 1: Gain Error tested at VREF = 2.0V, 2.5V, and 3.0V.

Note 2: ROUT tolerance is typically ±20%.

Note 3: Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.

Note 4: Reference input resistance is code dependent, minimum at 8555 hex.

Note 5: Slew-rate value is measured from 0% to 63%.

Note 6: Guaranteed by design. Not production tested.

Code = 0000 hex; CS = VDD; LDAC = 0;

SCLK, DIN = 0 to VDD levels

Major-carry transition

VIN = 0

Code = 0000 hex, VREF = 1Vp-p at 100kHz

Code = 0000 hex

Code = FFFF hex

(Note 6)

CONDITIONS

1.5

Power Dissipation

0.3

1.1

IDD

Positive Supply Current

4.75

5.25

VDD

Positive Supply Range

0.40

Hysteresis Voltage

CIN

Input Capacitance

mVp-p

nVs

DAC Glitch Impulse

Digital Feedthrough

µA

±1

IIN

Input Current

0.8

VIL

Input Low Voltage

2.4

VIH

Input High Voltage

Reference Feedthrough

SNR

Signal-to-Noise Ratio

120

CIN

Reference Input Capacitance

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

MAX542 (Note 6)

MAX542

(Note 6)

CONDITIONS

µs

VDD High to CS Low

(power-up delay)

tCL

SCLK Pulse Width Low

tCH

MHz

fCLK

SCLK Frequency

SCLK Pulse Width High

tLDACS

CS High to LDAC Low Setup

tLDAC

LDAC Pulse Width

tDH

DIN to SCLK High Hold

tDS

DIN to SCLK High Setup

tCSS0

CS Low to SCLK High Setup

tCSS1

CS High to SCLK High Setup

tCSH0

SCLK High to CS Low Hold

tCSH1

SCLK High to CS High Hold

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

Code = FFFF hex

MHz

Reference -3dB Bandwidth

DYNAMIC PERFORMANCE—REFERENCE SECTION

STATIC PERFORMANCE—DIGITAL INPUTS

POWER SUPPLY

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