2

ICS2510C

0010G—09/22/09

Pin Descriptions

Note:

1.

Weak pull-ups on these inputs

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1

AGND

PWR

Analog Ground

2, 10, 14

VCC

PWR

Power Supply (3.3V)

3

CLK0

OUT

Buffered clock output.

4

CLK1

OUT

Buffered clock output.

5

CLK2

OUT

Buffered clock output.

6, 7, 18, 19

GND

PWR

Ground

8

CLK3

OUT

Buffered clock output.

9

CLK4

OUT

Buffered clock output.

11

OE

1

IN

Output enable (has internal pull_up). When high, normal operation.

When low, clock outputs are disabled to a logic low state.

12

FBOUT

OUT

Feedback output

13

FBIN

IN

Feedback input

15

CLK5

OUT

Buffered clock output.

16

CLK6

OUT

Buffered clock output.

17

CLK7

OUT

Buffered clock output.

20

CLK8

OUT

Buffered clock output.

21

CLK9

OUT

Buffered clock output.

22

VCC

PWR

Power Supply (3.3V) digital supply.

23

AVCC

IN

Analog power supply (3.3V). When input is ground PLL is off and

bypassed.

24

CLKIN

IN

Clock input

Functionality

OE

AVCC

CLK (9:0)

FBOUT

Source

03.33

0

Driven

PLL

N

13.33

Driven

Driven

PLL

N

00

0

Driven

CLKIN

Y

1

0

Driven

Driven

CLKIN

Y

Test mode:

When AVCC is 0, shuts off the PLL

and connects the input directly to the output buffers

Buffer Mode

INPUTS

OUTPUTS

PLL

Shutdown