LM5025D

SNVSAB0 – JUNE 2015

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Pin Functions

PIN

DESCRIPTION

NAME

NO.

Analog ground. Connect directly to power ground. For the PW package option the exposed

AGND

11

G

pad is electrically connected to AGND.

Input to the pulse width modulator. An internal 5-k

Ω resistor pull-up is provided on this pin.

COMP

13

I

The external opto-coupler sinks current from COMP to control the PWM duty cycle.

Current sense input for cycle-by-cycle limiting. If CS1 exceeds 0.5 V the outputs will go into

CS1

3

I

cycle-by-cycle current limit. CS1 is held low for 50 ns after OUT_A switches high providing

leading edge blanking.

Current sense input for soft restart. If CS2 exceeds 0.5 V the outputs will be disabled and a

softstart commenced. The soft-start capacitor will be fully discharged and then released with

CS2

4

I

a pull-up current of 1 µA. After the first output pulse (when SS = 1 V), the SS charge current

will revert back to 20 µA.

Exposed pad, underside of the PW package option. Internally bonded to the die substrate.

EP

-

-

Connect to GND potential for low thermal impedance.

Main output driver. Output of the main switch PWM output gate driver. Output capability of 3-

OUT_A

8

O

A peak sink current.

Active Clamp output driver. Output of the active clamp switch gate driver. Capable of 1.25-A

OUT_B

9

O

peak sink current.

PGND

10

G

Power ground. Connect directly to analog ground.

RAMP

2

I

discharged at the conclusion of every cycle by an internal FET, initiated by either the internal

clock or the V x Sec clamp comparator.

Precision 5-V reference output. Maximum output current: 10 mA locally decouple with a 0.1-

REF

6

O

Oscillator timing resistor pin. An external resistor connected from RT to ground sets the

RT

14

I

internal oscillator frequency.

Soft-start control. An external capacitor and an internal 20-µA current source set the softstart

SS

12

I

ramp. The SS current source is reduced to 1 µA initially following a CS2 over-current event

or an over temperature event.

Oscillator UP/DOWN synchronization input. The internal oscillator can be synchronized to an

SYNC

15

I

external clock with a frequency 20% lower than the internal oscillator’s free running

frequency. There is no constraint on the maximum sync frequency.

TIME

5

I

between TIME and REF produces out-of-phase OUT_A and OUT_B pulses with deadtime.

Line Under-Voltage shutdown. An external voltage divider from the power source sets the

shutdown comparator levels. The comparator threshold is 2.5 V. Hysteresis is set by an

UVLO

16

I

internal current source (20 µA) that is switched on or off as the UVLO pin potential crosses

the 2.5 V threshold.

VCC

7

P

V. If an auxiliary winding raises the voltage on this pin above the regulation setpoint, the

internal start-up regulator will shutdown, reducing the device power dissipation.

Source input voltage. Input to start-up regulator. Input range 13 V to 90 V, with transient

VIN

1

I

capability to 105 V.

(1)

P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output

4

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