L8565G-S08-R datasheet(11/13 Pages) UTC

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L8565

Preliminary

LINEAR INTEGRATED CIRCUIT

UNISONICTECHNOLOGIESCO.,LTD

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www.unisonic.com.tw

QW-R114-004.d

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FUNCTIONAL DESCRIPTION(Cont.)

7. PWM Logic

The PWM logic block prioritizes the control input signals and generates the final logic signal to turn on the driver

stage. The speed of the logic gates in this block, together with the width of the reset pulse TOFF(MIN), are designed to

meet a maximum duty cycle DMAX of 95% at the GATE output under 133kHz of operation.

In case of high input currents which result in Peak Current Limitation, the GATE will be turned off immediately and

maintained in off state for the current PWM cycle. The signal TOFFMIN resets (highest priority, overriding other input

signals) both the current limit latch and the PWM on latch as illustrated in Fig. 13.

8. Voltage Loop

The voltage loop is the outer loop of the cascaded control scheme which controls the PFC output bus voltage VOUT.

This loop is closed by the feedback sensing voltage at VSENSE which is a resistive divider tapping from VOUT. The pin

VSENSE is the input of OTA1 which has an internal reference of 5V. Fig. 14 shows the important blocks of this voltage

loop.

8.1 Voltage Loop Compensation

The compensation of the voltage loop is installed at the VCOMP pin (see Fig. 14). This is the output of OTA1 and the

compensation must be connected at this pin to ground. The compensation is also responsible for the soft start

function which controls an increasing AC input current during start-up.

From

Full-wave

Retifier

VOUT

Current Loop

PWM Generation

VIN

Av(IIN)

Nonlinear

Gain

Gate Driver

GATE

VSENSE

VCOMP

OTA1

UTC L8565

Fig. 14 Voltage Loop

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