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LV2622L-S08-R 数据表(PDF) 6 Page - Unisonic Technologies |
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LV2622L-S08-R 数据表(HTML) 6 Page - Unisonic Technologies |
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6 / 8 page ![]() LV2622 Preliminary LINEAR INTEGRATED CIRCUIT UNISONICTECHNOLOGIESCO.,LTD 6 of 8 www.unisonic.com.tw QW-R102-045.a APPLICATION NOTES(Cont.) Power-Supply Bypassing and Layout The UTC LV2622 can apply for a single +2.5V~+5.5V supply or dual ±1.25V~±2.75V supplies. For single-supply operation, a 0.1µF ceramic capacitor should be placed close to the VDD pin to bypass the power supply VDD. For dual-supply operation, separate 0.1µF ceramic capacitors should be placed to the VDD and the VSS supplies to bypass them to ground, and 2.2µF tantalum capacitor for better performance. By decreasing the amount of stray capacitance at the op amp’s inputs and output, PC board l performance can be optimized. For example, placing external components as close to the device as possible can minimize trace lengths and widths. and using surface-mount components is a better way. For the operational amplifier, soldering the part to the board directly is strongly recommended. The EMI can be minimized because keeping the high frequency big current loop area small. Grounding A ground plane layer is important for UTC LV2622 circuit design. The length of the current path speed currents in an inductive ground return will create an unwanted voltage noise. Broad ground plane areas will reduce the parasitic inductance. Input-to-Output Coupling The input and output signal traces should not be parallel to minimize capacitive coupling. This helps reducing unwanted positive feedback. |
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