HIP2103, HIP2104

13

FN8276.0

November 27, 2013

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Functional Description

The following functional description references the “Block

Diagram” on page 2.

Overview

The HIP2103 has independent control inputs, LI and HI, for each

output, LO and HO. There is no logic inversion for these

input/output pairs. To minimize the possibility of shoot-through

failures of the bridge FETs caused by improper LI and HI signals

from an external controller, internal logic in the driver prevents

both outputs being high simultaneously. When either input is

high, the high input must go low before a high on the other input

propagates to its respective drive output. If both inputs are high

simultaneously, both output are low. If one input is high, followed

by the other input going high, the internal logic prevents any

shoot through. Note that the internal logic does not prevent

shoot-through if the dead-time provided by the external controller

is not sufficiently long as required by the turn-on/off times of the

bridge FETS.

If both inputs are high simultaneously for longer than 30µs, the

driver initiates a Sleep Mode to reduce the bias current to

minimize the battery drain. When in Sleep Mode, the HO output

is in a high-impedance state (2MΩ between HO and HS) and the

LO output is held low with an active 100Ω pull-down resistor. The

100Ω pull-down prevents inadvertent shoot-through resulting

from transients on the bridge voltage while both drivers are in the

Sleep Mode.

when VDD is less that the UV threshold. Sleep Mode is initiated if

UVLO is asserted for longer than 30µs.

The high-side driver bias is established by the boot capacitor

connected between HB and HS. The charge on the boot capacitor

is provided by the internal boot FET that is connected between

VDD and HB. The current path to charge the boot cap is enabled

(boot FET is on) when the drain voltage on the low-side bridge FET

(VHO) is <1V and when HO = 0. When the boot FET is on, the boot

The boot FET turns off when H0 = 1. The boot capacitor provides

the charge necessary to turn on the FET and maintains the bias

voltage on the high side driver for the duration of the period while

the FET is on. See the following for details on selecting the boot

capacitor value.

The peak charge current is limited in amplitude by the inherent

the boot cap voltage. Assuming that the on time of the low-side

FET is sufficiently long to fully charge the boot capacitor, the boot

drain-source of the low-side bridge FET).

When the HI input transitions high, the high-side bridge FET is

driven on. Because the HS node is connected to the source of the

high-side FET, the HS node rises almost to the level of the bridge

Because the boot capacitor voltage is referenced to the source

HS node. Simultaneously with HI = 1, the boot FET is turned off

preventing the boot capacitor from discharging back to VDD.

Because the high-side driver circuit is referenced to the HS node,

During the low to high transition of the phase node (HS), the boot

capacitor sources the necessary gate charge to fully enhance the

high-side bridge FET gate. After the gate of the bridge FET is fully

charged, the boot capacitor no longer sources charge to the gate

but continues to provide bias current to the high-side driver

through out the period while the high-side bride FET is on.

To prevent the voltage on the boot capacitor from drooping

excessively, the boot capacitor value must be sized appropriately.

If the boot voltage droops to the UVLO threshold, the high-side

FET is turned off to prevent damage due to insufficient gate

voltage.

FIGURE 19. LO OUTPUT RESISTANCE

-40

-20

0

20

40

60

80

100

120

140

TEMPERATURE (°C)

0

1

2

3

4

5

6

7

8

9

SOURCING

SINKING