U74HC4046AL-S16-R datasheet(11/19 Pages) UTC

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U74HC4046A

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

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www.unisonic.com.tw

QW-R502-461.C

PHASE COMPARATORS (Cont.)

Phase comparator 2 (PC2)

This is a positive edge-triggered phase and frequency detector. If the PLL is using the comparator, the loop is

controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. PC2 is

comprised of two D-type flip-flops, control-gating and a 3-state output stage. The circuit function is as an up-down

counter (Logic Diagram) for SIGIN causes an up-count and COMPIN causes a down-count.

The transfer function of PC2, assuming ripple (fr = fi) is suppressed, is

)

(

COMPIN

SIGIN

DEMOUT

−

where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC2OUT (via low-pass filter).

The phase comparator gain is:

)

V /

(

As shown in Fig.3, VDEMOUT is the resultant of the initial phase differences of SIGIN and COMPIN. Typical

waveforms for the PC2 loop locked at fo are shown in Fig.4.

Fig.3 Phase comparator 2: average output voltage versus input phase difference.

Fig.4 Typical waveforms for PLL using phase comparator 2, loop locked at fo.

If the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type

output driver at PC2OUT is held “ON” for a time corresponding to the phase difference (φDEMOUT). If the phase of

SIGIN lags that of COMPIN, the n-type driver is held “ON”.

If the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held “ON” for most of the

input signal cycle time, and for the remainder of the cycle both n and p-type drivers are “OFF” (3-state). If the

frequency of SIGIN is lower than that of COMPIN, the n-type driver that is held “ON” for most of the cycle. Then the

voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs

are equal in both phase and frequency. At this stable state the voltage on C2 remains constant as the PC2 output is

in 3-state and the VCO input at pin 9 is a high impedance. Also in the condition, the signal at the phase comparator

pulse output (PCPOUT) is a HIGH level, and it indicates a locked condition.

For PC2, there is no phase difference between SIGIN and COMPIN over the full frequency range of the VCO.

And as the low-pass filter, the power dissipation is reduced because both p and n-type drivers are “OFF” for most of

the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the

capture range and this is independent of the low-pass filter. The VCO adjusts to its lowest frequency via PC2 when

no signal present at SIGIN.

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