9

FN3086.6

July 21, 2005

Digital Section

Figures 6 shows the digital section for the ICL7136. In the

ICL7136, an internal digital ground is generated from a 6V

Zener diode and a large P-Channel source follower. This

supply is made stiff to absorb the relatively large capacitive

currents when the back plane (BP) voltage is switched. The

BP frequency is the clock frequency divided by 800. For

three readings/second this is a 60Hz square wave with a

nominal amplitude of 5V. The segments are driven at the

same frequency and amplitude and are in phase with BP

when OFF, but out of phase when ON. In all cases negligible

DC voltage exists across the segments.

The polarity indication is “on” for negative analog inputs. If IN

LO and IN HI are reversed, this indication can be reversed

also, if desired.

ICL7136

V+

BP

TEST

DECIMAL

POINT

SELECT

CD4030

GND

V+

TO LCD

DECIMAL

POINTS

FIGURE 5. EXCLUSIVE “OR” GATE FOR DECIMAL POINT DRIVE

FIGURE 6. ICL7136 DIGITAL SECTION

7

SEGMENT

DECODE

LCD PHASE DRIVER

LATCH

7

SEGMENT

DECODE

LOGIC CONTROL

INTERNAL

7

SEGMENT

DECODE

1000’s

100’s

10’s

1’s

TO SWITCH DRIVERS

FROM COMPARATOR OUTPUT

DIGITAL

GROUND

CLOCK

40

39

38

OSC 1

OSC 2

OSC 3

BACKPLANE

21

V+

TEST

V-

500

Ω

37

26

6.2V

COUNTER

COUNTER

COUNTER

COUNTER

1

†

ONLY ONE INVERTER SHOWN

FOR CLARITY

SEGMENT

OUTPUT

0.5mA

2mA

INTERNAL DIGITAL GROUND

TYPICAL SEGMENT OUTPUT

V+

c

a

b

c

d

f

g

e

a

b

a

b

c

d

f

g

e

a

b

c

d

f

g

e

ICL7136