LM49352 datasheet(79/106 Pages) TI

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LM49352

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SNAS467E – MARCH 2009 – REVISED MARCH 2013

DAC Effects Registers

Table 64. DAC_ALC_1 (0xA0h)

Bits

Field

Description

2:0

DAC_SAMPLE

This programs the timers on the ALC with the closest DAC sample rate.

DAC_SAMPLE

Expected DAC fS

000

8kHz

001

12kHz

010

16kHz

011

24kHz

100

32kHz

101

48kHz

110

96kHz

111

192kHz

LIMITER

If set, the circuit will never apply gain to the signal, no matter how small, but it will attenuate

the signal as soon as it reaches target and release it at the decay rate, once signal level

reduces below target. The I2C gain setting (at the time the LIMITER is enabled) is the

maximum gain that the ALC will apply. Care should be taken when choosing the optimum

I2C gain setting whenever enabling the Limiter.

STEREO LINK

If set, the ALC circuit uses the stereo average of the input signals to control the gain of the

stereo output. This maintains stereo imaging. If this bit is cleared, then both channels

operate as dual mono.

Table 65. DAC_ALC_2 (0xA1h)

Bits

Field

Description

3:0

NOISE_FLOOR

This sets the anticipated noise floor. Signals lower than the specified noise floor will be

gated from the ALC to avoid noise pumping.

NOISE_FLOOR

Noise Floor (dB)

0000

-39

0001

-42

0010

-45

0011

-48

0100

-51

0101

-54

0110

-57

0111

-60

1000

-63

1001

-66

1010

-69

1011

-72

1100

-75

1101

-78

1110

-81

1111

-84

NG_ENB

This enables the Noise Gate

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