24C32

DS21061F-page 4

© 1996 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

The 24C32 supports a bidirectional two-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, and a device

receiving data as receiver. The bus must be controlled

by a master device which generates the serial clock

(SCL), controls the bus access, and generates the

START and STOP conditions, while the 24C32 works

as slave. Both master and slave can operate as trans-

mitter or receiver but the master device determines

which mode is activated.

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is

not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this acknowledge

bit.

A device that acknowledges must pull down the SDA

line during the acknowledge clock pulse in such a way

that the SDA line is stable LOW during the HIGH period

of the acknowledge related clock pulse.

Of course,

setup and hold times must be taken into account. Dur-

ing reads, a master must signal an end of data to the

slave by NOT generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave (24C32) will leave the data line HIGH to

enable the master to generate the STOP condition.

Note:

The

24C32

does

not

generate

any

acknowledge bits if an internal program-

ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A)

(B)

(D)

(D)

(C)

(A)

START CONDITION

ADDRESS

OR

ACKNOWLEDGE

VALID

DATA ALLOWED

TO CHANGE

STOP

CONDITION