24LC024/24LC025

© 1997 Microchip Technology Inc.

Preliminary

DS21210A-page 7

6.0

WRITE OPERATIONS

6.1

Byte Write

Following the start signal from the master, the device

code(4 bits), the chip select bits (3 bits), and the R/W

bit which is a logic low is placed onto the bus by the

master transmitter. The device will acknowledge this

control byte during the ninth clock pulse. The next byte

transmitted by the master is the word address and will

be written into the address pointer of the 24LC024/

24LC025. After receiving another acknowledge signal

from the 24LC024/24LC025 the master device will

transmit the data word to be written into the addressed

memory location. The 24LC024/24LC025 acknowl-

edges again and the master generates a stop condi-

tion. This initiates the internal write cycle, and during

this time the 24LC024/24LC025 will not generate

acknowledge signals (Figure 6-1). If an attempt is made

to write to the protected portion of the array when the

hardware write protection (24LC024 only) has been

enabled, the device will acknowledge the command but

no data will be written. The write cycle time must be

observed even if the write protection is enabled.

6.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 24LC024/24LC025 in the

same way as in a byte write. But instead of generating

a stop condition, the master transmits up to 15 addi-

tional data bytes to the 24LC024/24LC025 which are

temporarily stored in the on-chip page buffer and will be

written into the memory after the master has transmit-

ted a stop condition. After the receipt of each word, the

four lower order address pointer bits are internally

incremented by one. The higher order four bits of the

word address remains constant. If the master should

transmit more than 16 bytes prior to generating the stop

condition, the address counter will roll over and the pre-

viously received data will be overwritten. As with the

byte write operation, once the stop condition is received

an internal write cycle will begin (Figure 6-2). If an

attempt is made to write to the protected portion of the

array when the hardware write protection has been

enabled, the device will acknowledge the command but

no data will be written. The write cycle time must be

observed even if the write protection is enabled.

6.3

WRITE PROTECTION

The WP pin (available on 24LC024 only) must be tied

ations to all address locations are allowed.

FIGURE 6-1:

BYTE WRITE

FIGURE 6-2:

PAGE WRITE

S

P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

A

R

T

S

T

O

P

CONTROL

BYTE

WORD

ADDRESS

DATA

A

C

K

A

C

K

A

C

K

S

P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

A

R

T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATA n + 15

S

T

O

P

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

DATA n +1