© 2006 Microchip Technology Inc.

DS21204E-page 11

25AA040/25LC040/25C040

3.7

Data Protection

The following protection has been implemented to

prevent inadvertent writes to the array:

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write or STATUS register

write, the write enable latch is reset

•CS must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle

is ignored and programming is continued

• The write enable latch is reset when the WP pin is

low

3.8

Power-On State

The 25XX040 powers on in the following state:

• The device is in low-power Standby mode

(CS = 1)

• The write enable latch is reset

• SO is in high-impedance state

• A low level on CS is required to enter active state

TABLE 3-3:

WRITE-PROTECT FUNCTIONALITY MATRIX

WP

WEL

Protected Blocks

Unprotected Blocks

STATUS Register

Low

X

Protected

Protected

Protected

High

0

Protected

Protected

Protected

High

1

Protected

Writable

Writable