PIC17C752 datasheet(21/328 Pages) MICROCHIP

21 / 328 page

DS30289A-page 21

PIC17C7XX

5.0

RESET

The PIC17CXXX differentiates between various kinds

of reset:

• Power-on Reset (POR)

• Brown-out Reset

• MCLR Reset

• WDT Reset

Some registers are not affected in any reset condition,

their status is unknown on POR and unchanged in any

other reset. Most other registers are forced to a “reset

state”. The TO and PD bits are set or cleared differently

in different reset situations as indicated in Table 5-3.

These bits, in conjunction with the POR and BOR bits,

are used in software to determine the nature of the

reset. See Table 5-4 for a full description of the reset

states of all registers.

When the device enters the "reset state" the Data

Direction registers (DDR) are forced set, which will

make the I/O hi-impendance inputs. The reset state of

some peripheral modules may force the I/O to other

operations, such as analog inputs or the system bus.

A simpliﬁed block diagram of the on-chip reset circuit is

shown in Figure 5-1.

Note:

While the device is in a reset state, the

internal phase clock is held in the Q1 state.

Any processor mode that allows external

execution will force the RE0/ALE pin as a

low output and the RE1/OE and RE2/WR

pins as high outputs.

FIGURE 5-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR

VDD

OSC1

WDT

Module

VDD rise

detect

OST/PWRT

On-chip

RC OSC†

WDT

Time_Out

Power_On_Reset

OST

10-bit Ripple counter

PWRT

Chip_Reset

10-bit Ripple counter

(Enable the PWRT timer

only during POR or BOR)

(If PWRT is invoked, or a Wake-up from

SLEEP and OSC type is XT or LF)

Reset

† This RC oscillator is shared with the WDT

when not in a power-up sequence.

BOR

Module

Brown-out

Reset

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