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PIC18F010 数据表(PDF) 21 Page - Microchip Technology |
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PIC18F010 数据表(HTML) 21 Page - Microchip Technology |
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21 / 176 page  2001 Microchip Technology Inc. Preliminary DS41142A-page 19 PIC18F010/020 FSR2H ---- 0000 ---- 0000 ---- uuuu FSR2L xxxx xxxx uuuu uuuu uuuu uuuu STATUS ---x xxxx ---u uuuu ---u uuuu TMR0H 0000 0000 0000 0000 uuuu uuuu TMR0L xxxx xxxx uuuu uuuu uuuu uuuu T0CON 1111 1111 1111 1111 uuuu uuuu OSCCON -000 00-0 -uuu uu-u -uuu uu-u LVDCON --00 0101 --00 0101 --uu uuuu WDTCON ---- ---0 ---- ---0 ---- ---u RCON(4,5) 0--1 11qq 0--q qquu u--u qquu IPR2 ---- 1111 ---- 1111 ---- uuuu PIR2 ---- 0000 ---- 0000 ---- uuuu(1) PIE2 ---- 0000 ---- 0000 ---- uuuu TRISB --11 1111 --11 1111 --uu uuuu LATB --xx xxxx --uu uuuu --uu uuuu PORTB --xx xxxx --uu uuuu --uu uuuu PSPCON ---- --00 ---- --00 ---- --uu EEADR xxxx xxxx uuuu uuuu uuuu uuuu EEDATA xxxx xxxx uuuu uuuu uuuu uuuu EECON2 ---- ---- ---- ---- ---- ---- EECON1 x--0 x000 u--0 u000 u--u uuuu OSCTUNE --00 0000 --qq qqqq --uu uuuu WPUB --11 1111 --11 1111 --uu uuuu IOCB --00 0000 --00 0000 --uu uuuu TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Power-on Reset, Brown-out Reset MCLR Reset WDT Reset Reset Instruction Stack Reset Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard- ware stack. 4: See Table 3-2 for RESET value for specific condition. 5: The long write enable is only reset on a POR or MCLR Reset. |
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