PIC17C752-08SLASHP datasheet(47/320 Pages) MICROCHIP

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Preliminary

DS30264A-page 47

PIC17C75X

7.2.2.1

ALU STATUS REGISTER (ALUSTA)

The ALUSTA register contains the status bits of the

Arithmetic and Logic Unit and the mode control bits for

the indirect addressing register.

As with all the other registers, the ALUSTA register can

be the destination for any instruction. If the ALUSTA

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Therefore, the result of an instruction with

the ALUSTA register as destination may be different

than intended.

For example, CLRF ALUSTA will clear the upper four

bits and set the Z bit. This leaves the ALUSTA register

as 0000u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF

and MOVWF instructions be used to alter the

ALUSTA register because these instructions do not

affect any status bit. To see how other instructions

affect the status bits, see the “Instruction Set Sum-

mary.”

The Arithmetic and Logic Unit (ALU) is capable of car-

rying out arithmetic or logical operations on two oper-

ands

single

operand. All

single

operand

instructions operate either on the WREG register or the

given file register. For two operand instructions, one of

the operands is the WREG register and the other one

is either a ﬁle register or an 8-bit immediate constant.

Note 3: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in sub-

traction. See the SUBLW and SUBWF

instructions for examples.

Note 4: The overﬂow bit will be set if the 2’s com-

plement result exceeds +127 or is less

than -128.

FIGURE 7-6: ALUSTA REGISTER (ADDRESS: 04h, UNBANKED)

R/W - 1

R/W - x

FS3

FS2

FS1

FS0

R = Readable bit

W = Writable bit

-n = Value at POR reset

(x = unknown)

bit7

bit0

bit 7-6:

FS3:FS2: FSR1 Mode Select bits

00 = Post auto-decrement FSR1 value

01 = Post auto-increment FSR1 value

1x = FSR1 value does not change

bit 5-4:

FS1:FS0: FSR0 Mode Select bits

00 = Post auto-decrement FSR0 value

01 = Post auto-increment FSR0 value

1x = FSR0 value does not change

bit 3:

OV: Overﬂow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overﬂow of the 7-bit magnitude,

which causes the sign bit (bit7) to change state.

1 = Overﬂow occurred for signed arithmetic, (in this arithmetic operation)

0 = No overﬂow occurred

bit 2:

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The results of an arithmetic or logic operation is not zero

bit 1:

DC: Digit carry/borrow bit

For ADDWF and ADDLW instructions.

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

Note: For borrow the polarity is reversed.

bit 0:

C: carry/borrow bit

For ADDWF and ADDLW instructions.

1 = A carry-out from the most signiﬁcant bit of the result occurred

Note that a subtraction is executed by adding the two’s complement of the second operand. For rotate

(RRCF, RLCF) instructions, this bit is loaded with either the high or low order bit of the source register.

0 = No carry-out from the most signiﬁcant bit of the result

Note: For borrow the polarity is reversed.

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