LP3852, LP3855

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SNVS174I – FEBRUARY 2003 – REVISED FEBRUARY 2015

Feature Description (continued)

9.3.6 ERROR Flag Operation

The LP3852 and LP3855 produce a logic low signal at the ERROR pin when the output drops out of regulation

due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The timing

diagram in Figure 17 shows the relationship between the ERROR flag and the output voltage. In this example,

the input voltage is changed to demonstrate the functionality of the ERROR Flag.

The internal ERROR comparator has an open drain output stage; thus, the ERROR pin should be pulled high

through a pullup resistor. Although the ERROR flag pin can sink current of 1 mA, this current is energy drain

from the input supply. Hence, the value of the pullup resistor should be in the range of 10 k

Ω to 1 MΩ. The

ERROR pin must be connected to ground if this function is not used. It should also be noted that when the

shutdown pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown

mode.

Figure 17. ERROR Operation

9.4 Device Functional Modes

9.4.2 Operation With SD Pin Control

A CMOS Logic low level signal at the SD pin will turn off the regulator. The SD pin must be actively terminated

through a 10-k

Ω pullup resistor for a proper operation.

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Product Folder Links: LP3852 LP3855