PIC16C925TSLASHCL datasheet(14/182 Pages) MICROCHIP

14 / 182 page

PIC16C925/926

DS39544A-page 12

Preliminary

 2001 Microchip Technology Inc.

2.2

Data Memory Organization

The data memory is partitioned into four banks which

contain the General Purpose Registers and the Special

Function Registers. Bits RP1 and RP0 are the bank

select bits.

The lower locations of each Bank are reserved for the

Special Function Registers. Above the Special Func-

tion Registers are General Purpose Registers imple-

mented as static RAM. All four banks contain special

function registers. Some “high use” special function

registers are mirrored in other banks for code reduction

and quicker access.

2.2.1

GENERAL PURPOSE REGISTER

FILE

The register file can be accessed either directly, or indi-

rectly

through

the

File

Select

FSR

(Section 2.6).

The following General Purpose Registers are not phys-

ically implemented:

• F0h-FFh of Bank 1

• 170h-17Fh of Bank 2

• 1F0h-1FFh of Bank 3

These locations are used for common access across

banks.

RP1:RP0

(STATUS<6:5>)

Bank

3 (180h-1FFh)

2 (100h-17Fh)

1 (80h-FFh)

0 (00h-7Fh)

PIC16C925T/CL 数据表(PDF) 14 Page - Microchip Technology

PIC16C925T/CL 数据表(HTML) 14 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载