PIC17C752-08SLASHCL datasheet(44/328 Pages) MICROCHIP

44 / 328 page

PIC17C7XX

DS30289A-page 44

7.2

Data Memory Organization

Data memory is partitioned into two areas. The ﬁrst is

the General Purpose Registers (GPR) area, and the

second is the Special Function Registers (SFR) area.

The SFRs control and provide status of device opera-

tion.

Portions of data memory are banked, this occurs in

both areas. The GPR area is banked to allow greater

than 232 bytes of general purpose RAM.

Banking requires the use of control bits for bank selec-

tion. These control bits are located in the Bank Select

region, the BSR bits are ignored. Figure 7-5 shows the

data memory map organization.

Instructions MOVPF and MOVFP provide the means to

move values from the peripheral area (“P”) to any loca-

tion in the register ﬁle (“F”), and vice-versa. The deﬁni-

tion of the “P” range is from 0h to 1Fh, while the “F”

range is 0h to FFh. The “P” range has six more loca-

tions than peripheral registers which can be used as

General Purpose Registers.

This can be useful in

some applications where variables need to be copied

to other locations in the general purpose RAM (such as

saving status information during an interrupt).

The entire data memory can be accessed either

directly or indirectly (through ﬁle select registers FSR0

and FSR1) (Section 7.4). Indirect addressing uses the

appropriate control bits of the BSR for accesses into

the banked areas of data memory. The BSR is

explained in greater detail in Section 7.8.

7.2.1

GENERAL PURPOSE REGISTER (GPR)

All devices have some amount of GPR area. The GPRs

are 8-bits wide. When the GPR area is greater than

232, it must be banked to allow access to the additional

memory space.

All the PIC17C7XX devices have banked memory in

the GPR area. To facilitate switching between these

banks, the MOVLR bank instruction has been added to

the instruction set. GPRs are not initialized by a

Power-on Reset and are unchanged on all other resets.

7.2.2

SPECIAL FUNCTION REGISTERS (SFR)

The SFRs are used by the CPU and peripheral func-

tions to control the operation of the device (Figure 7-5).

These registers are static RAM.

The SFRs can be classiﬁed into two sets, those asso-

ciated with the “core” function and those related to the

peripheral functions. Those registers related to the

“core” are described here, while those related to a

peripheral feature are described in the section for each

peripheral feature.

The peripheral registers are in the banked portion of

memory, while the core registers are in the unbanked

region. To facilitate switching between the peripheral

banks, the MOVLB bank instruction has been provided.

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