LP38853_15 datasheet(13/28 Pages) TI

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LP38853

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SNVS335D – DECEMBER 2006 – REVISED APRIL 2013

It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 k

Ω.

This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZ pole set by R1 and

CFF.

( (R1 x R2) / (R1 + R2) )

≤ 10 kΩ

(6)

Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%

capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will give

similar results.

Table 1.

VOUT

CFF

0.8V

1.07 k

Ω

1.78 k

Ω

12 nF

12.4 kHz

0.9V

1.50 k

Ω

1.87 k

Ω

8.2 nF

12.9 kHz

1.0V

1.00 k

Ω

1.00 k

Ω

12 nF

13.3 kHz

1.1V

1.65 k

Ω

1.37 k

Ω

8.2 nF

11.8 kHz

1.2V

1.40 k

Ω

1.00 k

Ω

10 nF

11.4 kHz

1.3V

1.15 k

Ω

715

Ω

12 nF

11.5 kHz

1.4V

1.07 k

Ω

590

Ω

12 nF

12.4 kHz

1.5V

2.00 k

Ω

1.00 k

Ω

6.8 nF

11.7 kHz

1.6V

1.65 k

Ω

750

Ω

8.2 nF

11.8 kHz

1.7V

2.55 k

Ω

1.07 k

Ω

5.6 nF

11.1 kHz

1.8V

2.94 k

Ω

1.13 k

Ω

4.7 nF

11.5 kHz

Please refer to the TI AN-1378 Application Report for additional information on how resistor tolerances affect the

calculated VOUT value.

INPUT VOLTAGE

The input voltage (VIN) is the high current external voltage rail that will be regulated down to a lower voltage,

which is applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever value is

used for VBIAS.

For applications where VBIAS is higher than 4.5V, VIN must be no greater than 4.5V, otherwise output voltage

accuracy may be affected.

BIAS VOLTAGE

The bias voltage (VBIAS) is a low current external voltage rail required to bias the control circuitry and provide

gate drive for the N-FET pass transistor. When VOUT is set to 1.20V, or less, VBIAS may be anywhere in the

operating range of 3.0V to 5.5V. If VOUT is set higher than 1.20V , VBIAS must be between 4.5V and 5.5V to

ensure proper operation of the device.

UNDER VOLTAGE LOCKOUT

The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is

below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V.

As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is

approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.

When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the

device will be functional, but the operating parameters will not be within the specified limits.

SUPPLY SEQUENCING

There is no requirement for the order that VIN or VBIAS are applied or removed.

One practical limitation is that the Soft-Start circuit starts charging CSS when both VBIAS rises above the UVLO

threshold and the Enable pin is above the VEN(ON) threshold. If the application of VIN is delayed beyond this point

the benefits of Soft-Start will be compromised.

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