TC510COG datasheet(12/28 Pages) MICROCHIP

12 / 28 page

TC500/A/510/514

DS21428B-page 12

7.0

DESIGN CONSIDERATIONS

7.1

Noise

The threshold noise (NTH) is the algebraic sum of the

integrator noise and the comparator noise. This value

is typically 30

µV. Figure 7-1 shows how the value of the

reference voltage can affect the final count. Such errors

can be reduced by increased integration times, in the

same way that 50/60Hz noise is rejected. The signal-

to-noise ratio is related to the integration time (TINT)

and the integration time constant (RINT) (CINT)asfol-

lows:

EQUATION 7-1:

7.2

System Timing

To obtain maximum performance from the TC5XX, the

overshoot at the end of the De-integration phase must

be minimized. Also, the Integrator Output Zero phase

must be terminated as soon as the comparator output

returns high. (See Figure 4-1).

Figure 4-1 shows the overall timing for a typical system

in which a TC5XX is interfaced to a microcontroller. The

microcontroller drives the A, B inputs with I/O lines and

monitors the comparator output, CMPTR, using an I/O

line or dedicated timer capture control pin. It may be

necessary to monitor the state of the CMPTR output in

addition to having it control a timer directly for the Ref-

erence De-integration phase. (This is further explained

below.)

The timing diagram in Figure 4-1 is not to scale, as the

timing in a real system depends on many system

parameters and component value selections. There

are four critical timing events (as shown in Figure 4-1):

sampling the input polarity; capturing the de-integration

time; minimizing overshoot and properly executing the

Integrator Output Zero phase.

7.3

Auto Zero Phase

The length of this phase is usually set to be equal to the

Input Signal Integration time. This decision is virtually

arbitrary since the magnitudes of the various system

errors are not known. Setting the Auto Zero time equal

to the Input Integrate time should be more than

adequate to null out system errors. The system may

remain in this phase indefinitely (i.e., Auto Zero is the

appropriate Idle state for a TC5XX device).

7.4

Input Signal Integrate Phase

The length of this phase is constant from one conver-

sion to the next and depends on system parameters

and component value selections. The calculation of

TINT is shown elsewhere in this data sheet. At some

point near the end of this phase, the microcontroller

should sample CMPTR to determine the input signal

polarity. This value is, in effect, the Sign Bit for the over-

all conversion result. Optimally, CMPTR should be

sampled just before this phase is terminated by chang-

ing AB from 10 to 11. The consideration here is that,

during the initial stage of input integration when the

integrator voltage is low, the comparator may be

affected by noise and its output unreliable. Once inte-

gration is well underway, the comparator will be in a

defined state.

7.5

Reference De-integration

The length of this phase must be precisely measured

from the transition of AB from 10 to 11 to the falling

edge of CMPTR. The comparator delay contributes

some error in timing this phase. The typical delay is

specifiedto be2

µsec. This should be considered in the

context of the length of a single count when

determining overall system performance and possible

single count errors. Additionally, Overshoot will result in

charge accumulating on the integrator after its output

crosses zero. This charge must be nulled during the

Integrator Output Zero phase.

VIN

tINT

30 x 10–6

(RINT)• (CINT)

S/N (dB) = 20 Log

•

(

)

TC510COG 数据表(PDF) 12 Page - Microchip Technology

TC510COG 数据表(HTML) 12 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载