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PIC16LC774-04/SP 数据表(PDF) 56 Page - Microchip Technology |
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PIC16LC774-04/SP 数据表(HTML) 56 Page - Microchip Technology |
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56 / 200 page ![]() PIC16C77X DS30275A-page 56 Advance Information © 1999 Microchip Technology Inc. FIGURE 8-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN AKSTAT AKDT AKEN RCEN PEN RSEN SEN R =Readable bit W =Writable bit U =Unimplemented bit, Read as ‘0’ - n =Value at POR reset bit7 bit0 bit 7: GCEN: General Call Enable bit (In I2C slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR. 0 = General call address disabled. bit 6: AKSTAT: Acknowledge Status bit (In I2C master mode only) In master transmit mode: 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5: AKDT: Acknowledge Data bit (In I2C master mode only) In master receive mode: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 1 = Not Acknowledge 0 = Acknowledge bit 4: AKEN: Acknowledge Sequence Enable bit (In I2C master mode only). In master receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3: RCEN: Receive Enable bit (In I2C master mode only). 1 = Enables Receive mode for I2C 0 = Receive idle bit 2: PEN: Stop Condition Enable bit (In I2C master mode only). SCK release control 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition idle bit 1: RSEN: Repeated Start Condition Enabled bit (In I2C master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition idle. bit 0: SEN: Start Condition Enabled bit (In I2C master mode only) 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition idle. Note: For bits AKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be written (or writes to the SSPBUF are disabled). |
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