LM3495MTCX datasheet(26/36 Pages) TI

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K =

PO + PTOTAL-LOSS

100

10k

100k

FREQUENCY (Hz)

-60

-40

-20

100

10k

100k

FREQUENCY (Hz)

-180

-160

-140

-120

-100

-80

-60

LM3495

SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013

www.ti.com

Figure 39. Overall Loop Gain and Phase

The bandwidth of this example circuit is 49 kHz, with a phase margin of 46°.

Efficiency Calculations

A reasonable estimation for the efficiency,

η, of a buck regulator controlled by the LM3495 can be obtained by

adding together the loss in each current carrying element, PTOTAL-LOSS, and using the equation:

(36)

The following shows an efficiency calculation to complement the Typical Application Circuit. Output power for this

circuit is PO = 1.2V x 10A = 12W. Input voltage is assumed to be 12V, and the calculations used assume that the

converter runs in CCM.

Chip Operating Loss

This term accounts for the current drawn at the VIN pin. This current, IIN, drives the logic circuitry and the power

FETs. The gate driving loss term from the power FET section of Design Considerations is included in the chip

operating loss. For the LM3495, IIN is equal to the steady state operating current, IQ, plus the FET driving current,

IGC. Power is lost as this IIN passes through the internal linear regulator of the LM3495.

IGC = (QG-HI + QG-LO) x fOSC

(37)

IGC = (11nC + 33nC) x 500 kHz = 22 mA

(38)

IQ is typically 1.8 mA, taken from the Electrical Characteristics table. Chip Operating Loss is then:

PQ = VIN x (IQ + IGC)

(39)

PQ = 12V x (1.8mA + 22mA) = 0.29W

(40)

High-Side FET Switching Loss

PSW = 0.5 x VIN x IO x (tR + tF) x fSW

(41)

PSW = 0.5 x 12V x 10A x (5 ns + 8 ns) x 500 kHz = 0.39W

(42)

FET Conduction Loss

PC = D (I

O x RDSON-HI x 1.3)

(43)

PC-HI = 0.1 x (100 x 0.013) = 0.13W

(44)

PC = (1 - D) (I

O x RDSON-LO x 1.3)

(45)

PC-LO = 0.9 x (100 x 0.0044) = 0.40W

(46)

RSNS Loss (if used)

PSNS = (1 - D) ((IO)

2 x R

SNS)

(47)

Not used in this example.

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