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数据搜索系统，热门电子元器件搜索 |
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TC835 数据表(PDF) 8 Page - Microchip Technology |
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TC835 数据表(HTML) 8 Page - Microchip Technology |
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8 / 24 page  TC835 DS21478B-page 8 © 2002 Microchip Technology Inc. FIGURE 3-2: SYSTEM ZERO PHASE 3.2.2 ANALOG INPUT SIGNAL INTEGRATION The TC835 integrates the differential voltage between the +INPUT and -INPUT pins. The differential voltage must be within thedeviceCommonmoderange (-1V from either supply rail, typically). The input signal polarity is determined at the end of this phase (see Figure 3-3). FIGURE 3-3: INPUT SIGNAL INTEGRATION PHASE 3.2.3 REFERENCE VOLTAGE INTEGRATION The previously charged reference capacitor is con- nected with the proper polarity to ramp the integrator output back to zero (see Figure 3-4). The digital reading displayed is: FIGURE 3-4: REFERENCE VOLTAGE INTEGRATION CYCLE 3.2.4 INTEGRATOR OUTPUT ZERO This phase guarantees the integrator output is at 0V when the system zero phase is entered and that the true system offset voltages are compensated for. This phase normally lasts 100 to 200 clock cycles. If an overrange condition exists, the phase is extended to 6200 clock cycles (see Figure 3-5). FIGURE 3-5: INTEGRATOR OUTPUT ZERO PHASE TABLE 3-1: INTERNAL ANALOG GATE STATUS + - +IN REF IN Analog Common – IN SWR SWIZ SWZ SWZ Integrator Switch Closed Switch Open SWRI+ Comparator To Digital Section Analog Input Buffer RINT CINT CREF CSZ SWRI- SWI SWZ SWRI+SWRI- SWI SW1 + - Analog Common – IN Integrator Switch Closed Switch Open Comparator To Digital Section Analog Input Buffer RINT CINT CREF CSZ SWI +IN SWRI+ SWRI- REF IN SWR SWZ SWI SW1 SWRI+SWRI- SWIZ SWZ SWZ Reading = 10,000 [Differential Input] VREF + - REF IN Analog Common – IN Integrator Switch Closed Switch Open Comparator To Digital Section Analog Input Buffer RINT CINT CREF CSZ SWRI+ SWRI+SWRI- SWRI- SWI SWI SW1 SWR SWZ SWIZ SWZ SWZ +IN + - + IN Analog Common – IN Integrator Switch Closed Switch Open Comparator To Digital Section Analog Input Buffer CREF SWI SWRI+ SWRI- REF IN SWR SWZ SWI SWRI+SWRI- SW1 SWIZ SWZ RINT CINT CSZ SWZ Conversion Cycle Phase SWI SWRI+SWRI-SWZ SWR SW1 SWIZ Reference Figures System Zero Closed Closed Closed Figure 3-2 Input Signal Integration Closed Figure 3-3 Reference Voltage Integration Closed* Closed Figure 3-4 Integrator Output Zero Closed Closed Figure 3-5 *Note: Assumes a positive polarity input signal. SWRI would be closed for a negative input signal. |
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