TC850 datasheet(14/26 Pages) MICROCHIP

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TC850

DS21479C-page 14

6.3

Pin Description (Digital)

6.3.1

CHIP SELECT AND CHIP ENABLE

(CS AND CE)

The CS and CE inputs permit easy interfacing to a vari-

ety of digital bus systems. CE is active LOW while CS

is active HIGH. These inputs are logically ANDed

internally and are used to enable the RD and WR

inputs.

6.3.2

WRITE ENABLE INPUT (WR)

The write input is used to initiate a conversion when the

TC850 is in Demand mode. CS and CE must be active

for the WR input to be recognized. The status of the

data bus is meaningless during the WR pulse, because

no data is actually written into the TC850.

6.3.3

READ ENABLE INPUT (RD)

The read input, combined with CS and CE, enable the

3-state data bus outputs. Also, in Continuous mode, the

rising edge of the RD input activates an internal byte

counter to sequentially read the three data bytes.

6.3.4

LOW/HIGH BYTE SELECT (L/H)

The L/H input determines whether the low (Least

Significant) Byte or high (Most Significant) Byte of data

is placed on the 3-state data bus. This input is mean-

ingful only when the TC850 is in the Demand mode. In

the Continuous mode, data must be read in three

predetermined bytes, so the L/H input is ignored.

6.3.5

OVERRANGE/POLARITY BIT

SELECT (OVR/POL)

The TC850 provides 15 bits of resolution, plus polarity

and overrange bits. Thus, 17 bits of information must be

transferred on an 8-bit data bus. To accomplish this, the

overrange and polarity bits are multiplexed onto data bit

DB7 of the Most Significant Byte. When OVR/POL is

HIGH, DB7 of the high byte contains the overrange sta-

tus (HIGH = analog input overrange, LOW = input within

full scale). When OVR/POL is LOW, DB7 is HIGH for

positive analog input polarity and LOW for negative

polarity. The OVR/POL input is meaningful only when

CS, CE and RD are active, and L/H is LOW (i.e., the

Most Significant Byte is selected). OVR/POL is ignored

when the TC850 is in Continuous mode.

6.3.6

CONTINUOUS/DEMAND MODE

INPUT (CONT/DEMAND)

This input controls the TC850 Operating mode. When

CONT/DEMAND is HIGH, the TC850 performs conver-

sions continuously. In Continuous mode, data must be

read in the prescribed sequence shown in Table 6-1.

Also, all three data bytes must be read within 443-1/2

internal clock cycles after the BUSY output goes low.

After 443-1/2 clock cycles data will be lost.

When CONT/DEMAND is LOW, the TC850 begins a

conversion each time CS and CE are active and WR is

being pulsed LOW. The conversion is complete and

data can be read after the falling edge of the BUSY out-

put. In Demand mode, data can be read in any

sequence and remains valid until WR is again pulsed

LOW.

6.3.7

BUSY OUTPUT (BUSY)

The BUSY output is used to convey an end-of-conver-

sion to external logic. BUSY goes HIGH at the begin-

ning of the de-integrate phase and goes LOW at the

end of the conversion cycle. Data is valid on the falling

edge of BUSY. The output-high period is fixed at 836

clock periods, regardless of the analog input value.

BUSY is active during Continuous and Demand mode

operation.

This output can also be used to generate an end-of-

conversion

interrupt

μP-based

systems.

Noninterrupt-driven

systems

can

poll

BUSY

determine when data is valid.

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