PIC16LC62BT-04ESLASHSP datasheet(8/120 Pages) MICROCHIP

8 / 120 page

PIC16C62B/72A

DS35008B-page 8

Preliminary

2.2

Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers and the

Special Function Registers. Bits RP1 and RP0 are the

bank select bits.

= 00

→ Bank0

= 01

→ Bank1

= 10

→ Bank2 (not implemented)

= 11

→ Bank3 (not implemented)

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers, implemented as

static RAM. All implemented banks contain Special

Function Registers. Some “high use” Special Function

Registers from one bank may be mirrored in another

bank for code reduction and quicker access.

2.2.1

GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly, or indi-

rectly

through

the

File

Select

FSR

(Section 2.5).

FIGURE 2-2:

RP1(1)

RP0

(STATUS<6:5>)

Note 1: Maintain this bit clear to ensure upward compati-

bility with future products.

Unimplemented data memory locations,

read as ’0’.

Note 1: Not a physical register.

These registers are not implemented on the

PIC16C62B, read as ’0’.

File

Address

File

Address

00h

INDF(1)

80h

01h

TMR0

OPTION_REG 81h

02h

PCL

82h

03h

STATUS

83h

04h

FSR

84h

05h

PORTA

TRISA

85h

06h

PORTB

TRISB

86h

07h

PORTC

TRISC

87h

08h

—

88h

09h

—

89h

0Ah

PCLATH

8Ah

0Bh

INTCON

8Bh

0Ch

PIR1

PIE1

8Ch

0Dh

—

8Dh

0Eh

TMR1L

PCON

8Eh

0Fh

TMR1H

—

8Fh

10h

T1CON

—

90h

11h

TMR2

—

91h

12h

T2CON

PR2

92h

13h

SSPBUF

SSPADD

93h

14h

SSPCON

SSPSTAT

94h

15h

CCPR1L

—

95h

16h

CCPR1H

—

96h

17h

CCP1CON

—

97h

18h

—

98h

19h

—

99h

1Ah

—

9Ah

1Bh

—

9Bh

1Ch

—

9Ch

1Dh

—

9Dh

1Eh

ADRES(2)

—

9Eh

1Fh

ADCON0(2)

ADCON1(2)

9Fh

20h

General

Purpose

Registers

General

Purpose

Registers

A0h

BFh

—

C0h

—

7Fh

—

FFh

Bank 0

Bank 1

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